• (5) As above, show the truth table, Boolean equation, and circuit diagram for a circuit that will take 5 inputs ABCDE and output a 1 if the pattern contains exactly 2 bits.

A B C D E |
----------------------
0 0 0 0 0 | 0
0 0 0 0 1 | 0
0 0 0 1 0 | 0
0 0 0 1 1 | 1
0 0 1 0 0 | 0
0 0 1 0 1 | 1
0 0 1 1 0 | 1
0 0 1 1 1 | 0
0 1 0 0 0 | 0
0 1 0 0 1 | 1
0 1 0 1 0 | 1
0 1 0 1 1 | 0
0 1 1 0 0 | 1
0 1 1 0 1 | 0
0 1 1 1 0 | 0
0 1 1 1 1 | 0
1 0 0 0 0 | 0
1 0 0 0 1 | 1
1 0 0 1 0 | 1
1 0 0 1 1 | 0
1 0 1 0 0 | 1
1 0 1 0 1 | 0
1 0 1 1 0 | 0
1 0 1 1 1 | 0
1 1 0 0 0 | 1
1 1 0 0 1 | 0
1 1 0 1 0 | 0
1 1 0 1 1 | 0
1 1 1 0 0 | 0
1 1 1 0 1 | 0
1 1 1 1 0 | 0
1 1 1 1 1 | 0

• F = ABC'D'E' + AB'CD'E' + AB'C'DE' + AB'C'D'E + A'BCD'E' + A'BC'DE' + A'BC'D'E + A'B'CDE' + A'B'CD'E + A'B'C'

Given F, which I derived from the unminimized boolean expression from the truth table, I'm supposed to create a a circuit diagram using only AND and OR gates. First of all, I can't figure out how to express NOT using just those two gates. Second, the diagram I came up with is so big and crappy looking that it just can't be right.

So anyway, if anyone is able to point me in the right direction or maybe fill me in on errors in logic I may have made it would be very helpful. Really, any constructive criticism on the matter would be awesome.

 

Why don't you give yourself a break and simplify this expression with a Karnaugh map? Do you know how to do it? Check here for a quick review:
http://www.allaboutcircuits.com/vol_4/chpt_8/11.html

It will result in a much smaller circuit and easier to debug.

 

I've read about them but in practice I had quite a difficult time actually making one so I kind of scrapped the idea and did it the way you see above. Honestly I'd like to learn about them but I don't think I have enough time between now and when the assignment is due to do it and do it right. Don't get me wrong though, I'm going to check that page out right now.

Also, in case anyone's curious, this isn't my entire assignment so please don't think I'm just trying to outsource my work or anything like that.

Edit: I cheated a bit and used a Karnaugh Map program to get the simplified expression, which is
F = A'B'CD'E + A'B'C'DE + A'B'CD'E + A'BC'DE' + A'BCD'E' + A'BC'D'E + ABC'D'E' + AB'C'DE' + AB'CD'E'

It reduced the number of AND gates by one, which is good, but I'm basically back at square one since now I must create a new diagram. I'll go ahead and do that now, and post the results.

 

Here's the modified diagram using the equation I got from the Karnaugh Map. Sorry for the double post but I thought it might be protocol since there's new subject information.

According to the equation, this diagram should be mostly correct. However, I am curious about the AND gates towards the right side of the circuit, specifically the ones that have 4 and 5 inputs and the one that hose connect to for output. My question is, should they be AND gates? Honestly I'm so braindead for working on the assignment this problem is from that I can't reason it out anymore. Is anyone able to tell me if an OR gate is the right choice? I'm completely new to circuit diagrams/logic gates so I'm a bit unclear on the subject.

Edit: Actually, I think I've determined correctly that OR gates should be used at locations I was talking about, since the equation is a string of ORs to begin with.

 

You are assuming correctly, but check this out. You need AND gates to connect the blue wires level, and after that only OR gates. BUT, you can use NAND for the first level and NAND for the second too, and that is equal to AND and OR. However the last gate with the 2-inputs must be an OR imperatively.
As for the NOT gates, you can make them with a 2-input NAND with the same signal tied to both inputs.

I 'm afraid I won't check the validity of your connections since the spaghetti of wires is too daunting for that.