Hi I am stuck at a problem in ASIC digital design: please help me out the problem is 1] This is a design question. Please design a counter that counts the number of times the number “5” appears in a 4-bit input stream. The I/O is as follows: NumberIn: 4-bits wide (input) Start: Reset counter and overflow flag to zero while start is high (input) Count: 8-bit unsigned count (of the number of “5”s that have occurred since start went low (output) Overflow: Goes high if count overflows (count is unsigned, so you only need to monitor the adder carry out) and stays high until reset is asserted. I want to see a Register Transfer Level (RTL) schematic. Design this functional unit at the RTL level. An adder is required – you can represent this as a “+” unit – no need to design its detail. There is no need to optimize the design. The only flip-flop you can use is a D flip-flop, and its clock input can only be connected to “clock”. You can NOT use a flip-flop with preset or clear. An exemplar timing diagram can be found below (x=unknown).