Hello everyone!

I am trying to design a flash ADC converter that measures voltage from 0 to 6 V with near 7-bit precision (my school assignment requires me to display the result on a 2 digit display : 01 to 99).
I have a general idea about the theory behind parallel conversion of voltage, but I still struggle to make the circuit work. My final goal is to cascade around 10 of these converter blocks, which consist of 10 comparators(9 for the second digit and the last for the first digit). But before that I need to make the display work, as the BCD converted data doesn't show up properly. Please advise.

I am new to electronics, so feel free if you have any other advice regarding this circuit.

 

I believe you are misinterpreting how an analog to digital converter works. You wont have two seperate "resistor ladders" for the digits, just one which will feed your encoder and result in a binary digit output. Your encoder is only 4 bits, resulting in a resolution of 6Volts/2^4 = 0.375Volts/step . If you want to increase the resolution, you can stack encoders putting the "ground" of one to the Vref of the next, resulting in an 8 bit encoder.
Regardless of how you do it, the output range will be 2^n, because your encoder is turning the resistor ladder into a n bit binary number. So you will probably need to use a microcontroller to convert this n bit range to 0 to 99. What kind of display is it?

 

Thank you for the response. I sort of managed to complete the circuit, but there are problems that need to be solved.

As you said the previous example is only 4 bit, but now I completed the circuit with 100 comparing op-amps which give me a reading from 1 to 99. Everything works more or less fine, except for the Vref (reference voltage of 6 V). The resistor ladder is made up of 100 resitors, each with a resistance of 1 kOhm and should cause a voltage drop of 0.06V per resistor.

That means that the reference voltage at the last comparator should be 0.06V, but the DC sweep analysis shows varying results, that are influence by the input voltage of the signal (I have included a graph of this example).
If the input voltage is around 1.5V I get the desired Vref of 0.06 V, but if I exceed the 1.5V mark, the Vref on the last comparator also changes.

P.S. The circuit is made up by lots of components and teh simulation runs very slowly on my computer (8 core 3.2 GHz). Is this normal or am I missing something here?

 

When you using that adc then you will need more input scale, but that is really a hard work, the way you used as what I'm trying to do for a simple LED O,scope, if you change to other method as using counter and DAC to do the job for ADC, you can using R-2R Ladder DAC, it's easier and it can be get more bits for the resolution as 8 bits to 256(0~255) digits.

Digital Ramp ADC.

R-2R Ladder DAC with LM358.

 

Three problems.

1. The comparators are powered by +4V, but the input signals can be as high as +6V. Change V4 to +9V.

2. The comparators are powered by -4V. You don't show the power supply for the digital logic circuits, but it probably is +5V or +3.3V. If all of the logic is CMOS, it can run on the same +9V as the comparators. In any case, the comparator output voltage must not go below the negative rail of the logic chips. Fortunately the LM224 has an input common mode range that includes its negative rail. Eliminate the V2supply and run everything from +9V and 0V.

3. In the detail drawing of one set of comparators, it looks like XSC2 output B is the signal input being converted. Why is XSC2 output A connected to the reference string? Also, The output return connections must go somewhere.

ak