What looks dangerous about it?
SgtWookie already indicated that the 10K resistive pull-up is too weak and suggested a totem-pole driver stage. If this is incorporated, I believe that it is a viable candidate. There may also be a few other nuances that need to be cleaned up. The 78S40 driver is a great chip--I have used it in numerous applications.

Well it has mains floating 100V without even a fuse powering a couple of ICs to begin with.

Your whole circuit floats at mains potential when you do stuff like this.

 

I mean I don't personally have a problem with these mains floating projects; in fact I have done a few of them myself. But it has gotta fused electrically and thermally, and they've gotta be built safe and applied to only the right applications.

 

The -10V, -16V rails are inherently impedance limited by the 10K shunt regulator source resistor in the lower left (Isc = 10mA). The diff amp is also impedance limited via the 2M input resistors. Nothing needs fusing. On the other hand, the total app would need to be evaluated as to what bad things could happen if the MOSFET blew its guts out.

 

There are some high speed gate drivers made by HP (now Avago) that are essentially high powered opto-couplers like the HCPL-3120.

http://www.avagotech.com/pages/en/o..._integrated_gate_drive_optocoupler/hcpl-3120/

The garden variety 4N series (e.g.) 4N37 are far too slow for PWM and lack output drive capability.

Hey Jim,

Consider me using the optocoupler as my gate driver now, would the bootstrap connection made for the previous IR2117 driver the same as for this optocoupler?

That is, Vb PIN of IR2117 equivalent to -> Vcc PIN of Optocoupler, and Vs PIN of IR2117 equivalent to -> Vee PIN?

Am I missing out something?

Datasheet of optocoupler: http://www.farnell.com/datasheets/652282.pdf
Datashee of IR2117: http://www.farnell.com/datasheets/59982.pdf

 

You might have a hard time getting it started--then it would run

 

The previous "bootstrap capacitor not charged" problem experienced with the IR2117 driver would be already eliminated since the bootstrap cap is already charged readily by Vcc and hence start-up shouldn't be a problem?

 

The previous "bootstrap capacitor not charged" problem experienced with the IR2117 driver would be already eliminated since the bootstrap cap is already charged readily by Vcc and hence start-up shouldn't be a problem?

Show us what progress you have made with the circuit or what you are now proposing so we can comment intelligently--in other words, post schematic(s)

 

Show us what progress you have made with the circuit or what you are now proposing so we can comment intelligently--in other words, post schematic(s)

Hi professionals,


Basically 3 main questions to address:

1. Could I connect the bootstrap circuit (see attached) for the optocoupler using the orginal designed circuitry for the IR2117 as attached in earlier post?
2. How would the adjacent diode of the free-wheeling as suggested in most bootstrap guides succeeds in preventing the Ve PIN not falling lower than the potential of (GND-Vf of the free-wheeling diode). Based on the fact that both Schottky are the same. Could it be because the free-wheeling diode (on the right) conducts more current than its neighbor diode (on the left) and hence the forward voltage drop of one diode would be higher than the other in nature?
3. Based on the datasheet of the optocoupler: http://www.farnell.com/datasheets/652282.pdf, should I add a resistor between point A & B (see attached) to 1) limit the input current and 2) lower the voltage drop to the recommended range of 1.5V?

Thanks in advance.

 

1. Forget the bootstrap power arrangement as i do not think it will work in your application (N-Channel high side switch). It is intended for half-bridge applications where the lower device can charge the upper device bootstrap capacitor.

What I recommend is that you look into an isolated DC-DC converter such as this 1W SIP manufactured by murata
http://search.digikey.com/us/en/products/MER1S1512SC/811-2134-5-ND/2175051

With this, life suddenly gets much easier.

Also, the gate resistor should go in series with the gate and not the source to prevent stray capacitances from messing with the gate voltage.

2. No longer applicable

3. Yes, you need to connect a series resistor to either side of the LED--do not design for the 1.5V LED drop as this tends to be variable, but for the desired LED current in your voltage source PWM generator. e.g. R = (5V source - 1.5V led) /10mA = 350Ω

If you follow this, you will have a rock-solid design that will work.
The only remaining issue besides the optimum PWM generation is voltage transients generated by free-wheeling diode recovery--this transient is a function of recoverd charge and softness of the turn-off di /dt --a snubber RC across the diode or inductor is generally used.

 

Hi Jim,

Thanks for your reply. But I am not allowed to buy the whole DC-DC converter unit as a whole as my main duty is to build one almost right from the scratch, that is, by building up my DIY Buck using as many discrete components as possible.

This is the primary reason why I seldom look at off-the-shelve DC-DC modules, and hence I hope I could find some useful guide (which I already did) to verify my design.

Thanks.

 

I think in this case the best solution is to add a lower MOSFET device--this one carries no power and is on only momentarily when power is applied or when the top device is off for a period of time--drive requirements are minimal and an isolated driver is not required and no heatsink is required--you must interlock the drive so that both top and bottom devices cannot conduct simultaneously (called common mode current or shoot through). When the lower device is on, the upper boot strap capacitor can charge.

2. Update: You should not need the 2nd schottky diode to protect the driver from this slight negative voltage--I have never seen this before anywhere and do not believe it is necessary or can even help the supposed situation.

 

I think in this case the best solution is to add a lower MOSFET device--this one carries no power and is on only momentarily when power is applied or when the top device is off for a period of time--drive requirements are minimal and an isolated driver is not required and no heatsink is required--you must interlock the drive so that both top and bottom devices cannot conduct simultaneously (called common mode current or shoot through). When the lower device is on, the upper boot strap capacitor can charge.

2. Update: You should not need the 2nd schottky diode to protect the driver from this slight negative voltage--I have never seen this before anywhere and do not believe it is necessary or can even help the supposed situation.

Hi Jim,

Foremost, the primary reason why I would like to build a non-sync buck instead of a sync buck is because I would like to verify that indeed the former has a higher efficiency operation than the latter when the converter o/p's current is > 1A. This is clearly stated in one of the research paper published in IEEE as can be seen in middle section of paragraph 2 of the Introduction in the attached pdf research paper.

I'll eventually build a synchronous buck for comparison purposes. If time permits, I'll try to build another buck with optocoupler as my gate driver and perhaps one last one with digital isolator gate driver as suggested by sgtwookie.

Next, while understanding that you're concern that the free-wheeling diode configuration would not be able to charge up the bootstrap capacitor, the guide (see attached - a cutout of the pdf) has mentioned that with the configuration as seen in Figure 23, (with a FW diode similar to mine), the charging path is still made possible for the bootstrap cap.






And if there is an explanation for this phenomenon, please verify if the following made sense:

• While a diode is conducting, it acts like a short circuit. Although the operating principle of a diode is to allow current to flow only in one direction, a relatively smaller current is still allowed to flow in the "reverse" direction as long as this current is not bigger than the forward biased current, that is, the net current throught the diode w.r.t the forward direction must remain >0. For example: If the FW biased current in a diode is about 5A due to one part of the circuit, and for whatsoever reason, there is another 1A current flowing in the reverse direction due to another part of the circuit, the net forward current would be 5-1= 4A and hence the diode will still operate, still conduct. Or to put it in other words, we could view it by using the superposition way. A 5A forward biased current superimpose with a 1A in the reverse direction through the same diode. One example for this superposition theory would be the mesh current analysis we are familiar with (see attached image).

Is my concept for why the the FW diode config would still charge up the bootstrap cap, correct?

Thanks.

.

 

OK, you are correct and I am wrong on this bootstrap stuff--hard to admit stupidity... My apology

What I did not realize is that when power is initially applied, the voltage across the output capacitor and load is zero--and this provides a return path for the bootstrap capacitor to charge--yes this (fig 23) is a viable technique--and I never had an issue with it not charging once repetitive operation has started.

Synchronous rectification using MOSFETs has
significant advantages in reducing this loss, so a variety of
circuits and analyses were studied, and MOSFETs suitable for
synchronous rectification were presented [4]. Due to the on
resistance used in an integrated SMPS converter is usually
about 300mΩ, the conduction voltage between the
synchronous MOSFET is beyond O.3V when the current
excesses IA. Compared with the forward conduction voltage
of Schottky diode, the conduction loss of synchronous
rectification is larger than Schottky diode beyond 1A load.

On the 1A value at which synchronous rectification becomes less efficient than schottky rectification, I disagree. Regarding the paragraph (above) in the paper cited, this logic is based upon a paper published in 1998 (note 4). MOSFET technology has advanced considerably since and continues to do so. At the present, 300mΩ may be considered a high Rdson. A little research on DigiKey's product search engine turned up perhaps a dozen 150V TO-220 N-Channel MOSFET devices with Rdson below 60mΩ--the best being 11mΩ (9.3mΩ typ).
http://www.irf.com/product-info/datasheets/data/irfb4115pbf.pdf

As a result, this transition is now in the range of 15 to 30A using 150V TO-220 devices--substantially higher using larger outlines (perhaps 100A), and higher yet with low voltage (<60V) devices (perhaps 300A).

Their logic for making such an arbitrary background statement may have been to avoid the requirement to include complex synchronous rectification in their research as the point of the paper is essentially an N-Channel MOSFET driver with an improved level translator.

Hope that this does not upset the apple cart.

 

Dear guys,

I've just built up my non-synchronous Buck converter. Both the schematic and the actual prototype on breadboard are attached.
After some testings, I am glad that the Buck is working from the range of duty cycle, D = 3% to 97% w/o the system going unstable. Although my orginal intention is to step down a 100V to 28V, I've put HV DC = 30V only for testing purposes. The step down ratio should be the same.

However one problem which I wish to clarify is when I was checking out the waveform of my Vs w.r.t. GND, could anyone explain why the Vs waveform has a single hump before it floats correctly to 30V. This phenomenon was also observed when I've measured the gate voltage (Vg, not Vgs) w.r.t. GND as well.

Could anyone advise what's wrong with here? Thank you.

Inductor datasheet (Model no. 2200LL-471-RC: http://www.bourns.com/data/global/pdfs/2200ll_series.pdf)
nMOS datasheet: (http://www.irf.com/product-info/datasheets/data/irf640n.pdf)

 

It's due to the current through L1 being discontinuous.

Have a look at the attached simulation of your circuit.

Note that as the current through L1 passes through zero, V(s) goes positive.

You should also be made aware that at about 400uS after the circuit starts, current through L1 peaks at nearly 7 Amperes; nearly twice L1's rating. This is because there are no provisions for a soft start. L1 would saturate, and basically appear to be a straight piece of wire while current was so high.

Also, since you have no provisions for feedback, your output voltage will be dependent on your load current.

 

I agree with SgtWookie--you can help it by either increasing inductance or frequency

 

Well, increasing inductance will increase the peak current if there is no feedback, and the output voltage will start to overshoot considerably.

Our OP really needs to monitor both the output voltage, and the current through the MOSFET, D2 or the inductor, and adjust the duty cycle of the MOSFET accordingly.

The closer L1's current gets to the maximum current rating, the lower effective inductance that it will have. This is difficult to simulate; the simulation I've posted has a fixed 470uH inductance and a 92m Ohm resistance.

 

Well, increasing inductance will increase the peak current if there is no feedback, and the output voltage will start to overshoot considerably.

Our OP really needs to monitor both the output voltage, and the current through the MOSFET, D2 or the inductor, and adjust the duty cycle of the MOSFET accordingly.

The closer L1's current gets to the maximum current rating, the lower effective inductance that it will have. This is difficult to simulate; the simulation I've posted has a fixed 470uH inductance and a 92m Ohm resistance.

Exactly! It was only after I made a call to the manufacturer that I realised that the inductance of my model drops to only 187.5uH under rated current condition. This value is very far away from 470uH.

Hence, from here, we could see that the inductance is a function of current, that is, it is dependent of current. Not to mention its ESR too. I believe it would be the same.

 

It's due to the current through L1 being discontinuous.

Have a look at the attached simulation of your circuit.

Note that as the current through L1 passes through zero, V(s) goes positive.

You should also be made aware that at about 400uS after the circuit starts, current through L1 peaks at nearly 7 Amperes; nearly twice L1's rating. This is because there are no provisions for a soft start. L1 would saturate, and basically appear to be a straight piece of wire while current was so high.

Also, since you have no provisions for feedback, your output voltage will be dependent on your load current.

Is it right to say that why the current through L does swing to negative is because that is actually the Schottky diode reverse recovery current?

And the other answer which I want to know is since the main nMOS is off during about 2.8-10us, that is, the load circuit is being disconnected away from the HV rail during this est. 7.2us interval, why does the V(s) swing till close to almost 45V and not close to the o/p 14V?

 

Is it right to say that why the current through L does swing to negative is because that is actually the Schottky diode reverse recovery current?

No. The "camel hump" occurs AFTER the inductor is discharged and the diode ceases conducting. It's a result of the inductor and the output cap being series resonant. See the attached simulation; I stopped the gate signal after 58 pulses. The time frame I zeroed in on was right after the startup was complete.

And the other answer which I want to know is since the main nMOS is off during about 2.8-10us, that is, the load circuit is being disconnected away from the HV rail during this est. 7.2us interval, why does the V(s) swing till close to almost 45V and not close to the o/p 14V?

It's due to the resonance of L1 and the output capacitor being in series.