When I look at the data sheets for the P-Channel MOSFET's the Vgs is rated from -2V min to about -4, or -4.5 V max. So shouldn't I be holding the gate voltage to about 4 volts of the source?

What are you talking about here, the threshold voltage?

You need to get Vgs below the threshold voltage (closer to 0v) in order to turn it off.
You need to get Vgs to the value where Id is specified in order to turn it fully on.

 

Yes I was referring to the Vgs Threshold. So Vgs(th) is where the MOSFET's start turning on and their optimimum Vgs is shown where they rate for Drain current, Id? -10v in the case of the IRF4905PbF? Ok, it's starting to make sense. Thanks.

When the battery is nearly fully charged voltage will be around 14V and the panel still has, at best, 22V so Vgs will only be about 8 there but that should be ok from an efficiency point of view since you're throwing away most of the panel's power at that point anyway. Could it damage the MOSFET if Vgs runs at 8, or say even 4 or 5? That will probably be increasing the RdsOn correct? Which will mean the MOSFET will burn the energy as heat? Meaning having to dissipate 10's of watts?

 

Yes I was referring to the Vgs Threshold. So Vgs(th) is where the MOSFET's start turning on and their optimimum Vgs is shown where they rate for Drain current, Id? -10v in the case of the IRF4905PbF?

Yes.
You have to have Vgs below (closer to 0v) the minimum threshold voltage for the MOSFET to be considered turned OFF.
You have to have the Vgs at the Id-rating specified voltage in order to be considered turned fully on.

When the battery is nearly fully charged voltage will be around 14V and the panel still has, at best, 22V so Vgs will only be about 8 there but that should be ok from an efficiency point of view since you're throwing away most of the panel's power at that point anyway. Could it damage the MOSFET if Vgs runs at 8, or say even 4 or 5? That will probably be increasing the RdsOn correct? Which will mean the MOSFET will burn the energy as heat? Meaning having to dissipate 10's of watts?

When the MOSFET is turned ON, Vgs won't be lower (closer to 0) than the battery bank voltage less the Vbe of Q2. So, if your batteries are heavily discharged at 11.4v, Vbe is 0.7v, your MOSFET Vgs will still be around -10.7v.

[eta]
Do you understand why that is?

 

I guess I really don't understand how you get the -10.7 voltage and exactly what causes Q1 and Q2 to operate. I tried looking at the current in LTSpice across the Q1 and Q2 and they both plots looked the same. Do Q1 and Q2 stay steady state while Q3 is On or do they switch constantly in an analog balancing act, like a voltage follower? How does the 12V Zener get to 10, or 10.7 volts?

I added a schematic which I think is current as per this thread. Is the second 12V Zener between Gate and Source oriented correctly?

The scope pic is showing Vgs (the gate is the top plot, source on the bottom). The Vgs (or delta of the cursors) is 8.00 because I have that 10V Zener in there, but I don't know how to calculate those two volts between the Zener voltage and the Vgs.

 

OK, I take it back - worst case is -8v when the battery bank is at 12v and the solar panel is pulled down to the battery voltage. If the battery bank is discharged below 12v, the Vgs will decrease further when on, mainly due to the ratio of R2 and R3.

Increasing the value of R2 would help that, but would slow the turn-off time.

Changing R3/Q3 to a switchable 3ma-5mA current sink (like a current mirror) would probably fix that. Perhaps someone else will help you with that; I'm running out of time to do so.

 

I'm not really concerned about the VGS when the battery get's low.

Do Q1 and Q2 stay steady state while Q3 is On or do they switch constantly in an analog balancing act, like a voltage follower? How does the 12V Zener get to 10, or 10.7 volts?

 

I'm not really concerned about the VGS when the battery gets low.

Do Q1 and Q2 stay steady state while Q3 is On or do they switch constantly in an analog balancing act, like a voltage follower?

Q1 and Q2 are wired as a common-emitter voltage follower.
They amplify the current that's on their bases.
The voltage on their bases varies between Solar_In when Q3 is off, and up to (Solar_In - 12v) when Q3 is ON.

How does the 12V Zener get to 10, or 10.7 volts?

R2 and R3 also act like a voltage divider when there isn't enough "headroom" from the MOSFET source terminal to ground.

Haven't you run the simulation I posted? You really could answer some of these questions yourself by trying it out.

I don't mean to be short with you - it's just that very soon I'll be off the board for what may be quite a while, and you'll have to either hope that someone else will help you, or figure it out yourself.

 

I hope all is well with you and thanks for your help so far.

 

Finally got a PCB with this design. I guess this one was literally on the slow boat from China. It doesn't have the caps or 2nd Zener that was added later to cure the ringing and voltage spike on the gate. It will be interesting to see how much different the performance is on this vs the breadboard. I can always solder the caps to the relevant leads.

http://www.flickr.com/photos/20841173@N08/5622838201/