high impedance and noise margin

Discussion in 'General Electronics Chat' started by twainerm, Nov 30, 2013.

  1. twainerm

    Thread Starter New Member

    Nov 30, 2013
    3
    0
    Hi,
    I am reading Digital Integrated Circuits by Rabaey. As per book - cmos has high input impedance and that helps in cmos to get high noise margin.
    I understand why cmos has high input impedance and I understand what is noise margin but I am not able to understand how does having high input impedance help in high noise margin.
    Please can one you help me understand this.
    Regards,
    Twain
     
  2. crutschow

    Expert

    Mar 14, 2008
    13,009
    3,233
    I don't understand either. CMOS logic has a high digital noise margin because the logic threshold voltage is near 1/2 the supply voltage. That has nothing to do with a high input impedance, so I think that book is incorrect if that is what it states.
     
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