Hello all,
To give a little bit of background, I am working on this design project and the goal is to build a single-stage amplifier that performs linearly without clipping under a certain set of constraints. I am very familiar with small-signal analysis and have no problem solving problems, but this project has been keeping me busy for quite some time now, and I am hoping that someone can lend a hand.
The amplifier is constrained by it's output swing, gain, output load, input resistance, power supply, and DC power dissipation.
I really just want to know if my approach in designing this amplifier makes sense, rather than just getting someone to design it for me. That's partly why I don't want to post the values of the restrictions. But some important information about the restrictions is that the gain is very small, (less than 5), and phase isn't an issue, the output load is small, (less than 1k), the max output amplitude is less than 0.5 V, and the DC power dissipation is less than 0.5 W. Probably would have been easier to post my values, but again, I am not looking for someone to tell me how to build this, I just need to know if I'm on the right path.
We are using an NPN 2N3904 BJT, and I have tried both the emitter bypassed and not bypassed with no luck on making a circuit that performs properly. For my current attempt at this, I am designing this amp with a bypassed emitter. Since we are given the gain, as well as the maximum output amplitude on the load, we are able to find the maximum input swing:
|gain| = |vo|/|vin| = gm*RL (bypassed emitter)
We are given the gain, and RL, so the small-signal transconductance is just:
gm = |gain|/RL
We also know that gm = vt*Ic = 40*Ic (room temperature)
Therefore, Ic = gm/40, so now we have to work with that.
Now this is the part where I get stuck. To continue on with the design, an assumption of beta (hfe, current gain) has to be made in order to calculate input terminal resistance (rpi) as well as the base current (Ib). When I read the datasheet: http://www.fairchildsemi.com/ds/2N/2N3904.pdf there seems to be so much variance in the current gain, for different Ic and Vce values. I know what my Ic is, based on calculations above, but is my next step to force my transistor to be biased for a certain Vce on the data sheet to maintain a good value for hfe? For instance, say my Ic was 10 mA, and looking at the typical current gain vs. Ic plot, it shows that hfe is roughly 225 at Vce = 5 V and Ic = 10 mA. Should I make sure that my transistor is DC biased so that Vce is 5 V, to ensure a consistent hfe?
From there, the next problems lies in finding the four-resistor network values, which I am having trouble with calculating. For the base resistors that bias the base voltage between power and ground, should I assume that the current passing through them is significantly greater than Ib and just perform a voltage division to have the correct value placed on Vb to bias the transistor?
I just don't know what approach to take when designing this, probably because I am not that experienced with all this stuff yet.
Hopefully I didn't lose you guys, but I appreciate those who made it this far in the post and can actually help me out.
Thanks a lot,
Blah
To give a little bit of background, I am working on this design project and the goal is to build a single-stage amplifier that performs linearly without clipping under a certain set of constraints. I am very familiar with small-signal analysis and have no problem solving problems, but this project has been keeping me busy for quite some time now, and I am hoping that someone can lend a hand.
The amplifier is constrained by it's output swing, gain, output load, input resistance, power supply, and DC power dissipation.
I really just want to know if my approach in designing this amplifier makes sense, rather than just getting someone to design it for me. That's partly why I don't want to post the values of the restrictions. But some important information about the restrictions is that the gain is very small, (less than 5), and phase isn't an issue, the output load is small, (less than 1k), the max output amplitude is less than 0.5 V, and the DC power dissipation is less than 0.5 W. Probably would have been easier to post my values, but again, I am not looking for someone to tell me how to build this, I just need to know if I'm on the right path.
We are using an NPN 2N3904 BJT, and I have tried both the emitter bypassed and not bypassed with no luck on making a circuit that performs properly. For my current attempt at this, I am designing this amp with a bypassed emitter. Since we are given the gain, as well as the maximum output amplitude on the load, we are able to find the maximum input swing:
|gain| = |vo|/|vin| = gm*RL (bypassed emitter)
We are given the gain, and RL, so the small-signal transconductance is just:
gm = |gain|/RL
We also know that gm = vt*Ic = 40*Ic (room temperature)
Therefore, Ic = gm/40, so now we have to work with that.
Now this is the part where I get stuck. To continue on with the design, an assumption of beta (hfe, current gain) has to be made in order to calculate input terminal resistance (rpi) as well as the base current (Ib). When I read the datasheet: http://www.fairchildsemi.com/ds/2N/2N3904.pdf there seems to be so much variance in the current gain, for different Ic and Vce values. I know what my Ic is, based on calculations above, but is my next step to force my transistor to be biased for a certain Vce on the data sheet to maintain a good value for hfe? For instance, say my Ic was 10 mA, and looking at the typical current gain vs. Ic plot, it shows that hfe is roughly 225 at Vce = 5 V and Ic = 10 mA. Should I make sure that my transistor is DC biased so that Vce is 5 V, to ensure a consistent hfe?
From there, the next problems lies in finding the four-resistor network values, which I am having trouble with calculating. For the base resistors that bias the base voltage between power and ground, should I assume that the current passing through them is significantly greater than Ib and just perform a voltage division to have the correct value placed on Vb to bias the transistor?
I just don't know what approach to take when designing this, probably because I am not that experienced with all this stuff yet.
Hopefully I didn't lose you guys, but I appreciate those who made it this far in the post and can actually help me out.
Thanks a lot,
Blah
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