# Help with PLL circuits

Discussion in 'General Electronics Chat' started by Geeky, Oct 7, 2013.

1. ### Geeky Thread Starter New Member

Oct 7, 2013
3
0
Hi guys,

How are you all? I am trying to build to a PLL circuits. As part of the circuit, I will need an offset adder, integrator, rectifier, and another stage of offset adder.

I havent done circuits for very long time. So please bear with me if Im crapping.

I have designed the first stage offset adder and integrator.

Please see attached diagrams. Schematic 1 is the circuit for offset adder which basically a summing amplifier, and then the second stage op-amp is the integrator.

The AC source with 1 Vac, is passed through the R3 and R1, R3 will later be a variable resistor when I transfer this to PCB.

From the diagram, I dont understand how the 5V added by V2 becomes 2.5V at the output of U1 (first Op-amp). I tried calculating it out, but could not get the exact point. Please advice.

Then, at the second stage. If you see the frequency response diagram. The 3dB is approximately at 200 kHz. But by using 1/2$\prod$RC formula, R=R3 and C=C1, which are 1 kohm and 50 pF, respectively, the cutoff should be approximately 3.1 MHz. So I dont really get it. Please advice if Im in the right direction, or the equivalent circuit calculation is wrong.

Please point where Im going wrong. I have also attached the time domain graph.

Thank you so much.

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2. ### LvW Active Member

Jun 13, 2013
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Geeky, a first and short look onto your diagram reveals that the last stage (integrator) is in saturation because of the dc part that appears at the integrator input.

Jun 22, 2012
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4. ### Geeky Thread Starter New Member

Oct 7, 2013
3
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Hi guys. Thanks for your feedback.

With regard to Dodgydave comment, I have a found XR-2211A as a PLL IC, see attached datasheet.

http://www.farnell.com/datasheets/7277.pdf

The datasheet provides the circuit construction for tone detection, and I need that. But however, it is unclear how could I tap out the VCO output, cause that is what I need, I need the locked VCO output.

5. ### w2aew Member

Jan 3, 2012
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absf and eyesee like this.
6. ### Brownout Well-Known Member

Jan 10, 2012
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You don't need to tap the VCO. The Locked Detect and FSK outputs are pined out.

May 28, 2009
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Here's a few things that may help you get started with PLL. You could do a google search for specifics of what knowledge you seek.

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• ###### cardinal_phase_lock_loop_basics.pdf
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absf likes this.
8. ### Geeky Thread Starter New Member

Oct 7, 2013
3
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Hi w2aew, brilliant video! Helped me a lot! Thanks for that.

I have building the circuit in practical as well. Its working fine. But I have a small problem, please see the attached schematic.

So the signal goes through a summing amp, integrator, full wave rectifier and final summing amp. All the sections are working fine. But after full wave rectifier (Op amp U4), there a is a DC offset. I dont want that DC offset. Because I would like to add DC through the final stage of summing amp from 0V to any arbitrary +V. So how can I remove the DC, I dont want any inline capacitor. Im thinking of buffer, will that be the correct move?