Help with multiplexer

Discussion in 'Homework Help' started by arcsky, May 16, 2009.

  1. arcsky

    Thread Starter Member

    Apr 17, 2009
    12
    0
    Hi all electronic gurus.
    Today i want help with multiplexers.

    Task 1.
    Draw logic diagram for a multiplex, which has input signal A and B, and control signal S. The output
    bait included with U. multiplexes to be built with as few two-inputs NAND-gates
    as possible. It shall apply to the output Y = A for S = 1 and Y = B for S = 0.

    Task 2.
    To a four-to-one (4:1) multiplex is input I3 I2 I1 I0 connected. Selection signals are S1
    and S0, where S1 is the most significant bit. Enter the Boolean expression for output signal U, then
    insignalena I3 I2 I1 I0 linked by:
    I3 3, I2 to 2, I1 to 1, and I0 to 0.
    Note:. Multiplex has inputs 3, 2, 1 and 0

    Thanks in advance!

    Best regards Arcsky
     
  2. mik3

    Senior Member

    Feb 4, 2008
    4,846
    63
    Post your work up to now and we will help you to correct it if it is wrong.
     
  3. arcsky

    Thread Starter Member

    Apr 17, 2009
    12
    0
    The problem is i dont understand how to solve it.
     
  4. mik3

    Senior Member

    Feb 4, 2008
    4,846
    63
    You have to try rather saying I don't understand.
     
  5. arcsky

    Thread Starter Member

    Apr 17, 2009
    12
    0
    Task to i solved now, wasnt so hard.
    Please help me little with task 1.
     
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