Help with Mealy and Moore Machines

Thread Starter

thisguy692

Joined Jul 27, 2008
5
this is what i have so far but still having some trouble

architecture behavemealy of MEALYmachine is
begin
process (clk)
begin
if (clk’event and clk=‘1’) then
current_state <= next_state;
end process;
process (current_state, x)
case current_state is
when “00” => if (x=‘0’) then next__state <= “01”;
else next_state <= “00”;
when “01” => if (x=‘0’) then next__state <= “00”;
else next_state <= “00”;
when “10” => if (x=‘1’) then next__state <= “10”;
else next_state <= “00”;
end case;
end if;
end process;
process (current_state, x)
begin
out_sig <= current_state and x
end process;
end behavioural;
 

Thread Starter

thisguy692

Joined Jul 27, 2008
5
Well i am supposed to make a mealy and moore machine that reads the sequence of '1010' in vhdl and in verilog. i am having a little trouble understanding how to write the code for both of these. what i wrote earlier is what i have so far but its not running. any help would be appreciated in either vhdl and verilog.
 

roddefig

Joined Apr 29, 2008
149
Well, I don't remember what the difference was between the two types but here is how I would write a state machine in Verilog.

Rich (BB code):
module state_machine (clk, rst, seq_in, out)

input clk, rst, seq_in;
output out; reg out;

reg [1:0] state;

always @(posedge rst or posedge clk) begin
    if (rst == 1'b1) begin
        state <= 2'b00;
        out <= 1'b0;
    end else begin
        case (state)
            2'b00: begin
                out <= 1'b0;
                if (seq_in == 1'b1) begin
                    state <= 2'b01;
                end
            end
            2'b01: begin
                if (seq_in == 1'b0) begin
                    state <= 2'b10;
                end else begin
                    state <= 2'b00;
                end
            end
            2'b10: begin
                if (seq_in == 1'b1) begin
                    state <= 2'b11;
                end else begin
                    state <= 2'b00;
                end
            end
            2'b11: begin
                if (seq_in == 1'b0) begin
                    out <= 1'b1;
                    state <= 2'b00;
                end else begin
                    state <= 2'b01;
                end
            end
        endcase
    end
end
endmodule
Note that if we get the sequence "1011" we do not reset to the start state, instead we reset to state 01. This is because we could get something like "1011010" in which case if we reset to state 00 it would not be recognized as valid.

I don't believe we wrote synchronous state machines in my digital logic class, but this should at least be able to give you the general idea. I never write asynchronous state machines in production code.
 
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