Any help would be welcome in creating a mealy or moore machine for the sequence of 1010 in VHDL and Verilog.
module state_machine (clk, rst, seq_in, out)
input clk, rst, seq_in;
output out; reg out;
reg [1:0] state;
always @(posedge rst or posedge clk) begin
if (rst == 1'b1) begin
state <= 2'b00;
out <= 1'b0;
end else begin
case (state)
2'b00: begin
out <= 1'b0;
if (seq_in == 1'b1) begin
state <= 2'b01;
end
end
2'b01: begin
if (seq_in == 1'b0) begin
state <= 2'b10;
end else begin
state <= 2'b00;
end
end
2'b10: begin
if (seq_in == 1'b1) begin
state <= 2'b11;
end else begin
state <= 2'b00;
end
end
2'b11: begin
if (seq_in == 1'b0) begin
out <= 1'b1;
state <= 2'b00;
end else begin
state <= 2'b01;
end
end
endcase
end
end
endmodule
by Duane Benson
by Jake Hertz
by Aaron Carman
by Jake Hertz