Help with Mealy and Moore Machines

Discussion in 'Homework Help' started by thisguy692, Jul 27, 2008.

  1. thisguy692

    Thread Starter New Member

    Jul 27, 2008
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    Any help would be welcome in creating a mealy or moore machine for the sequence of 1010 in VHDL and Verilog.
     
  2. Dave

    Retired Moderator

    Nov 17, 2003
    6,960
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    Please read.

    Dave
     
  3. thisguy692

    Thread Starter New Member

    Jul 27, 2008
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    this is what i have so far but still having some trouble

    architecture behavemealy of MEALYmachine is
    begin
    process (clk)
    begin
    if (clk’event and clk=‘1’) then
    current_state <= next_state;
    end process;
    process (current_state, x)
    case current_state is
    when “00” => if (x=‘0’) then next__state <= “01”;
    else next_state <= “00”;
    when “01” => if (x=‘0’) then next__state <= “00”;
    else next_state <= “00”;
    when “10” => if (x=‘1’) then next__state <= “10”;
    else next_state <= “00”;
    end case;
    end if;
    end process;
    process (current_state, x)
    begin
    out_sig <= current_state and x
    end process;
    end behavioural;
     
  4. roddefig

    Active Member

    Apr 29, 2008
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    0
    What's the problem? If you're having trouble writing the code I might be able to help out.
     
  5. thisguy692

    Thread Starter New Member

    Jul 27, 2008
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    0
    Well i am supposed to make a mealy and moore machine that reads the sequence of '1010' in vhdl and in verilog. i am having a little trouble understanding how to write the code for both of these. what i wrote earlier is what i have so far but its not running. any help would be appreciated in either vhdl and verilog.
     
  6. roddefig

    Active Member

    Apr 29, 2008
    149
    0
    Well, I don't remember what the difference was between the two types but here is how I would write a state machine in Verilog.

    Code ( (Unknown Language)):
    1.  
    2. module state_machine (clk, rst, seq_in, out)
    3.  
    4. input clk, rst, seq_in;
    5. output out; reg out;
    6.  
    7. reg [1:0] state;
    8.  
    9. always @(posedge rst or posedge clk) begin
    10.     if (rst == 1'b1) begin
    11.         state <= 2'b00;
    12.         out <= 1'b0;
    13.     end else begin
    14.         case (state)
    15.             2'b00: begin
    16.                 out <= 1'b0;
    17.                 if (seq_in == 1'b1) begin
    18.                     state <= 2'b01;
    19.                 end
    20.             end
    21.             2'b01: begin
    22.                 if (seq_in == 1'b0) begin
    23.                     state <= 2'b10;
    24.                 end else begin
    25.                     state <= 2'b00;
    26.                 end
    27.             end
    28.             2'b10: begin
    29.                 if (seq_in == 1'b1) begin
    30.                     state <= 2'b11;
    31.                 end else begin
    32.                     state <= 2'b00;
    33.                 end
    34.             end
    35.             2'b11: begin
    36.                 if (seq_in == 1'b0) begin
    37.                     out <= 1'b1;
    38.                     state <= 2'b00;
    39.                 end else begin
    40.                     state <= 2'b01;
    41.                 end
    42.             end
    43.         endcase
    44.     end
    45. end
    46. endmodule
    47.  
    Note that if we get the sequence "1011" we do not reset to the start state, instead we reset to state 01. This is because we could get something like "1011010" in which case if we reset to state 00 it would not be recognized as valid.

    I don't believe we wrote synchronous state machines in my digital logic class, but this should at least be able to give you the general idea. I never write asynchronous state machines in production code.
     
    Last edited: Aug 4, 2008
  7. thisguy692

    Thread Starter New Member

    Jul 27, 2008
    5
    0
    Thanks a lot for the help. It makes sense now. Thanks again
     
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