Help with logic please

Discussion in 'General Electronics Chat' started by BillyJ, May 18, 2015.

  1. BillyJ

    Thread Starter New Member

    Dec 11, 2012
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    I have been trying to get my head round this for a while now but I can't seem to get it to work.

    My specifications:

    4 Inputs
    1 reset
    1 output
    ^^^^^^ times 4

    inputs are active low
    reset is active high


    I want my system to default to output HIGH when all the inputs are HIGH and if any inputs are LOW then I want my system to output LOW and hold that value forever, until the reset is pressed where it will again output HIGH if all the inputs are HIGH. also, if the reset is held HIGH it would be nice for the output to be held HIGH also although this feature is not necassery.

    I was using some dual 4 input NAND gates and some D type flip-flops but I would really like to know how you guys would go bout this problem avoiding a micro controller and preferably using 4000 series logic?

    Thank you in advance for your help,
    Billy
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    Can you think of a logic gate that is LO when all of the input signals are HI and that goes HI if any one of them goes LO?

    With that in mind, think about how a DFF behaves in terms of the clock signal and the clear (reset) input compared to what you want.

    How are these four input signals produced?
     
  3. MrChips

    Moderator

    Oct 2, 2009
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    Connect the output of the NAND gate to the CLOCK input of the D-type flip-flop.
    Connect the D-input to logic HIGH (Vdd).
    Connect the SET input to GND (Vss)
    Connect the RESET input to a switch to Vdd. Pull-down the RESET input with a 10kΩ resistor to GND (Vss).
    Connect all unused inputs to GND (Vss).
    Leave all unused output unconnected.
     
  4. BillyJ

    Thread Starter New Member

    Dec 11, 2012
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    The four signals come from a battery monitor with an open collector output and are pulled up with a 10k resistor

    And your first question, a 4 input NAND, which is what I was using, the latching is the harder bit, I don't think I fully understand how DFFs behave.
     
  5. WBahn

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    Mar 31, 2012
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    A basic DFF has four inputs and two outputs. The D input is the usual data input. The CLK input is the clock and on each rising edge of the clock input whatever value is present on the D input is captured and is reflected on the Q and Qbar outputs. The D input that is captured is mirrored on the Q output while the Qbar output is the opposite.

    The other two inputs are asynchronous inputs which means that there effect takes place immediately. The Set input immediately "captures" a HI value (takes Q HI and Qbar LO) while a Reset input does the opposite.
     
  6. BillyJ

    Thread Starter New Member

    Dec 11, 2012
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    The way I initially did it, was to have the output from the NAND go into the set of the DFF and the reset go to the reset, with what you've said, why didn't this work? perhaps because I left the D and CLK floating?
     
  7. WBahn

    Moderator

    Mar 31, 2012
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    Leaving the D and CLK input floating can very easily cause erratic behavior, particularly in CMOS circuits. Unused inputs should NEVER be left floating (again, particularly in CMOS circuits).

    The Set and Reset inputs of most standard flip flops is active-LO, meaning that you want the signal to go LO when you want to Set (or Reset) the chip.

    Which part, exactly, are you using?
     
  8. BillyJ

    Thread Starter New Member

    Dec 11, 2012
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    What do you mean by which part?

    Also, if I were leaving the inputs not connected, would I set the unused ones all LOW?
     
  9. MrChips

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    Oct 2, 2009
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    All unused inputs must be connected to logic LOW or logic HIGH.
    Which one will depend on the function and polarity sense of the specific input. Check the datasheet to determine which is the correct logic level.
     
    Last edited: May 18, 2015
  10. BillyJ

    Thread Starter New Member

    Dec 11, 2012
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    Thanks guys, and MrChips, your solution worked perfectly so thanks again!
     
  11. WBahn

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    Mar 31, 2012
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    Which DFF are you using? It will have a part number such as 74HC74 or CD4013.

    Which way you connect unused inputs depends on the input. For instance, if you are using a 4-input NAND gate but only had three input signals, you would tie the unused one HI because that does not interfere with using the other three inputs as a 3-input NAND gate. But if you are using a 4-input NOR gate but only had three input signals, you would tie the unused one LO. Do you see why?
     
  12. BillyJ

    Thread Starter New Member

    Dec 11, 2012
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    I do see why, isn't it similar to path sensitisation?

    Also, I'm using an cd4013be
     
  13. WBahn

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    Mar 31, 2012
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    I don't recall hearing the term "path sensitization" so I'm not sure.

    The CD4013 is active-HI on the Set/Reset.

    http://pdf.datasheetcatalog.com/datasheets/228/108664_DS.pdf

    How were you setting up your Reset signal? Were you pulling it down when not actively resetting it, or was it just floating?
     
  14. BillyJ

    Thread Starter New Member

    Dec 11, 2012
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    it was pulled down, and if something is active high, would I pull it low, and vice versa?
     
  15. MrChips

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    Ask yourself what is the active state and what is the idle state.
    You want a resistor to pull the input into the idle state.

    For multi-input gates, you need to consider the function of the gate with respect to its inputs.
    In such a situation unused inputs need to be in the active state for the other inputs to have an effect.
     
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