Help with Logic Circuit/Delay

Discussion in 'The Projects Forum' started by robby991, Dec 18, 2008.

  1. robby991

    Thread Starter Active Member

    Dec 17, 2007
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    Cheers everyone. I have a problem with a circuit and I need some help. I posted this a while back but I have not had much time to work on it since then. I designed the attached circuit but it is not quite doing what I wat it to do. It works like this:

    The clock drives this logic circuit that passes through a tri state buffer. This tri state buffer (74241) is continuously help open by a D flip flop (7474) to ensure the path for the clock is always open. There is a point in my state machine logic circuit where 4 outputs are high, which drives a 4 input AND gate. This passes through an inverter, to generate low signal, where I send the signal 2 separate ways.

    1) To the CLR pin of the 7474 (low signal triggers clr on 7474) which sets the output Q low which turns off the tri state buffer.

    2) Through a delayed pulse circuit using 2 555 timers which is also triggered on the falling clock edge (first 555 serves as delay and second generates the output pulse) which produces a high pulse after 1.1RC. Once this pulse is generated it passes through another inverter to the Flip Flop which turns the output back high and tri state buffer back on.


    The idea is the tri state buffer is turned off, then after the delayed pulse it turns back on.


    The problem is the following. Once the low signal comes out of the first inverter after the AND gate, it turns the tri state buffer off as it should so no more clock signnal can get through. However, the delay pulse is not getting triggered at the same time because the tri state buffer remains off. It is like the tristate buffer is turned off before the delayed pulse (2 555 timers) can be triggered. I even put an LED at the output of the AND gate,and it remains on once the tristate buffer is turned off.

    The delay circuit works fine if I don't connect the output of the inverter after the AND gate to the CLR pin of the D Flip Flop.

    I know this may seem confusing, but does anyone have any ideas why my delay circuit won't work when the circuit is completed? Any suggestions would be great! Thank you very much!!!!
     
  2. mik3

    Senior Member

    Feb 4, 2008
    4,846
    63
    Can you explain what is the problem more clearly.
     
  3. robby991

    Thread Starter Active Member

    Dec 17, 2007
    79
    0
    I think I know what the problem is but I am not sure how to fix it, it has to do with the 555 triggering on my delay circuit. It is set up to trigger on the low edge. Does the 555 trigger on a low pulse going from high-->low-->high again? Because my circuit goes from high to low, then gets stuck at low because the low signal turns off the tri state buffer and will not allow the clock to retun back high again. So the input at the 555 is not seeing the high->low-->high cycle so it won't trigger, and the delayed pulse is not produced. Is this the problem? How can I fix it?
     
  4. eblc1388

    Senior Member

    Nov 28, 2008
    1,542
    102
    You have missed the finer point of using 555 as a monostable. While this might not apply to normal monostable ICs, in case of 555, "The trigger signal must not be longer than the output".

    555trigx.png

    So you need to place a capacitor in the triggering input of the first 555 and hopefully this will solve your problem.
     
  5. robby991

    Thread Starter Active Member

    Dec 17, 2007
    79
    0
    Ok thanks I will try thisand see if it works.
     
  6. robby991

    Thread Starter Active Member

    Dec 17, 2007
    79
    0
    Thanks eblc1388, I added a 2nF cap where you said and it works great! I understand how the trigger signal must not be longer than the output, but how does this capacitor fix this?

    Also, the output of my timer (after inverter) does not trigger the PR1 pin to make the output Q go high again and turn on the tri state buffer. Does my pulse width haave to be a certain length to trigger these 74 series ics? Currently, I have 1.1(158k*.86uF) which is 149 ms. Could this be the problem?
     
  7. eblc1388

    Senior Member

    Nov 28, 2008
    1,542
    102
    The addition of the capacitor shaped the logic level change into a pulse so the monostable works.

    Now the 555 part of your circuit is working, I would like to point out that your use of the 7474 in the current connection would create an illegal state in the 7474 where both /PRE and /CLR are LOW. This state is unstable and not desirable as described in the data sheet.

    A better way to tackle the problem is to preset the 7474 during power ON into a known state, with Q output HIGH so the tri-state buffer is enabled. Once the multi-input AND gate detects the correct logic HIGH condition on all its input, its output will goes HIGH. This will trigger the first 555.

    [​IMG]

    You can also use this logic change to clock the 7474. By placing a LOW on D input, this clocking will clock the "D" level into the Q, so Q is now LOW, disabling the tri-state buffer.

    After the first 555 completes its timing, the second 555 will be triggered. When the second 555 times out, its output goes LOW and this will preset the 7474 into the initial power ON state, with its output Q HIGH. Now the tri-state buffer is re-enabled.

    I think this is what you've wanted. Do you absolutely need the second 555? What is its purpose?

    If not, the tri-state buffer can be re-enabled after the first 555 times out. You can do that simply by removing the parts inside the red boundary and joining "A" & "B" together.
     
  8. robby991

    Thread Starter Active Member

    Dec 17, 2007
    79
    0
    EBLC1388. Thank you very much for your help, my circuit works as it should. I removed the second 555, like you said, as I didnt really need it. I just activated the tri state buffer when the 1st 555 went low.

    However the DFF Q output is not high when I power on my board like you said it should be. I looked at the truth table and saw that the only time Q is high (when D is low) is when PR is low and CLR is high. So I grounded PR via 10k resistor. However, now when I run my circuit, the buffer is not re-enabled after the 555 (ie. Q does not return high). How can I configure this to get Q high upon power up and still have my circuit work??
     
  9. robby991

    Thread Starter Active Member

    Dec 17, 2007
    79
    0
    Sorry that may have been confusing. What I am trying to say is I don't see how Q will be high upon power up when looking at the truth table. CLR and PR are high, D is low. CLK is low (or floating) before AND is enabled.
     
  10. eblc1388

    Senior Member

    Nov 28, 2008
    1,542
    102
    Its is the first row in the logic truth table where /PR should be LOW to set Q high.

    I previously rely on the large value 10K resistor and 100nF of capacitor to pull /PR LOW during power up and obviously it does not work. This can be fixed via an external power ON reset circuit.

    I would give you two options. Either a change of configuration or an additional power ON reset circuit.

    In the following circuit, the changed connections are /PR, /CLR , D and /Q. You need to move the tri-state buffer enable from 7474 Q to 7474 /Q output. On the other circuit, an inverter is used to generate a Power On reset signal.

    [​IMG]

    [​IMG]
     
    Last edited: Jan 9, 2009
  11. robby991

    Thread Starter Active Member

    Dec 17, 2007
    79
    0
    Configurations are good eblc3188, thank you. Tried both a decided to go for the former because it is simpler. Thank you!

    Just out of curiosity, how did you chose the values for the 420uf cap and 120k resistor? What is the logic behind this? I don't quite understand it.
     
  12. eblc1388

    Senior Member

    Nov 28, 2008
    1,542
    102
    The selection of 120Ω is to make the TTL inverter input logic LOW after the power ON reset operation.

    Selection of the 470uF is just a convenient value not too large for practical usage, chosen because of the very low value of R in the RC time constant.
     
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