Help with designing last stage of a 3 stage amplifier (CS, ER, ER)

Discussion in 'Homework Help' started by clbeav, May 2, 2011.

  1. clbeav

    Thread Starter New Member

    Jan 28, 2011
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    Hey guys, I'm stuck trying to design the last stage of a 3 stage amplifier. The amplifier is a MOSFET to BJT to BJT amplifier with the stages Commons Source to Emitter Resistor to Emitter Resistor. This amplifier is completely open with only a few restrictions (like given load and input resistance for the circuit and total voltage gain).

    Using the 12Vdc given supply, 2k Ohm load, and total voltage gain (at least 100 overall), I've decided to shoot for 5 v/v out of each stage. I designed the two Emitter Resistor stages, but I'm stuck when I get to the MOSFET stage (the first stage). The reason why it must be MOSFET is that I need a high impedance on the input (200k Ohms). I have the input resistance for the 2nd stage, but wasn't quite sure where I need to go from here. I'm using 2n7000 for the MOSFET and 3904 for the BJT stages.

    I've refrained from giving out too many values, since I don't want anyone doing the work for me, I just need a little guidance on how to start the MOSFET stage (I'm still not great at reading the MOSFET datasheet and deciding which values are which in the formulas). Do I need to pull the values from the graphs on the datasheet or the chart? So confused here.
     
  2. R!f@@

    AAC Fanatic!

    Apr 2, 2009
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    Welcome...

    No schematics....I am lost..
     
  3. clbeav

    Thread Starter New Member

    Jan 28, 2011
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    Np, here's the schematic I was aiming for however I'm having trouble with the first stage and was just inputting values in. Essientially I'm trying to find the resistor values for voltage divider bias for the MOSFET, and the source and drain resistors. (R10, R11, R12, & R13). I designed this amplifier from teh last stage back since the load was given. My target gain for each stage is 5. The Emitter Resistor on the last stage (R3) was 200, I just changed it to try and fix some clipping, but it should be 200.
     
  4. R!f@@

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    What are you trying to achieve exactly..

    What should be ur end result?
     
  5. t_n_k

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    Mar 6, 2009
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    Understand your reluctance to post the design criteria - you want to do the work yourself. That's a good work ethic.

    However, it would help if we (forum members) had some notion of what you are required to achieve in the overall design.

    The design of the last two stages seems to lack some "finesse" - but that's all part of the learning process.

    I think you could probably have wrapped the two final stages as a single stage common emitter design - your target stage gains are very modest. Also the voltage divider biasing for those stages isn't what I would consider as reasonable. You could probably do better there - particularly to limit loading of previous stages.

    As a rule of thumb, the typical bias current for the divider network should be about 10x the BJT base current.
     
    Last edited: May 2, 2011
  6. t_n_k

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    Mar 6, 2009
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    You mentioned a target gain of 5 per stage.

    Your mosfet stage is going to have a gain very much greater than 5 - more like 300-400.

    In terms of setting up the bias for this stage you need a value of gm and Gate-to-Source threshold voltage to work with. One data sheet for the 2N7000 quotes a value of 100mS at Id=0.2A. But that's all pretty "rubbery". Also the Vgs threshold value has a rather large variability - from 0.8V to 3V. Take a mean estimate of Vgs(th)=1.9V.????

    Suppose you take these as indicative.

    To find Id you then have the requirements

    Id=gm(Vgs-Vgs(th)) and Vgs=Vb-IdRs where Vb is the divider bias voltage.

    You probably want Vds=Vcc/2=6V (say)

    So Id=6/(Rs+Rd)=6/24k=250uA.

    Vgs-Vgs(th)=Id/gm=250uA/0.1A/V=2.5mV

    Vgs=Vgs(th)+2.5mV=1.9V+2.5mV

    So Vgs is close enough to 1.9V.

    Vs=4k*Id=1V

    Requiring Vg=Vb=2.9V

    This would mean a value of R11≈0.32*R10

    With R10=1M this gives R11=320K which is close enough to what you have.

    As I said this is all pretty rubbery.
     
  7. clbeav

    Thread Starter New Member

    Jan 28, 2011
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    First off, this is just an amplifier design with some specs given. There's no real application here such as hooking the amplifier up in real life other than testing. This is a project that is for learning. the main specs are 2k Ohm load and 100 V/V gain. I have to calculate a feedback circuit too, but this was just for the main circuit. I'm not worried about getting a circuit to work per say, I was mainly worried about calculating the resistor values of the MOSFET (CS) stage. Anyone can sit down in multisim all day and plug and chug resistor values until they get a clean signal. I was wanting something that was mainly done on paper before simulation.

    You were exactly right t_n_k, I cut out one of the stages and the gain is right around where I want it now. However, i did want to keep the Emitter Resistor without the bypass capacitor since I want a Class A output with little distortion or clipping.

    Here's how I went about calculating the circuit for the last stage

    RL = 2k Ohms, Set Rc = RL Assume β = 150, Vbe = 0.7v, temp = 26 °C, Vcc = 12v

    Av = (-RL || Rc)/Re + re, designing for a 5 gain, Av was set to 5. Re+re was assumed to be Re if Re is much greater than re.

    so I got 1k/5 = 200Ω.

    Since design, Rb = 0.1βRe = 3000.

    Rac = (Rc || RL) +Re = 1.2kΩ
    Rac = Re = RL = 2.2kΩ

    Icq = Vcc/(Rac+Rdc) = 3.53 mA

    Vbb = Vbe + Icq(Rb/β + Re) = 1.48V

    check re:

    re = 26mv/Icq = 7.4 Ω, so assumption of Re being much greater than re is fine.

    R1 = Rb/ (1 - Vbb/Vcc) = 3.5kΩ (rounded up)
    R2 = Rb(Vcc)/Vbb = 24.5kΩ (rounded up)

    Rin = Rb (re + Re) / (Rb/β + re + Re) = 2.7kΩ

    Now how do I go about calculating the resistors for the MOSFET common source stage. I'm stuck here. The only thing that's given is that the input impedance must be greater than 200kΩ which means RG needs to be greater than 200kΩ, which pretty much tells me that R1 and R2 (the voltage divider bias resistors) need to be greater than 200kΩ since the parallel combination needs to be greater than 200kΩ. I just don't know how to proceed about getting the values for Rs and Rd.

    Here's an updated circuit that works but this is me just messing around with resistor values for the first stage and adjusting my Rc on the second stage for a little more gain.

    EDIT - sorry t_n_k pretty much answered my question, didn't read his entire response before I got a little post happy to update everyone on the progress.

    Pretty much need Vgs and gm from the datasheet, didn't know if there was another way of going about it though.
     
    Last edited: May 3, 2011
  8. clbeav

    Thread Starter New Member

    Jan 28, 2011
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    Yea that's the major problem I had. These datasheets give large ranges of values and it's almost impossible to predict what they will actually do when tested in the lab.

    That being said, I'm just going to do some calculations and simulate, and I will probably still stick with the 2 stage design that I had, since the output was clean and the gain met spec.
     
  9. t_n_k

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    Mar 6, 2009
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    The FET input design in post #7 is not very good.

    I would suggest something more like the attachment which meets the specs quite well. Gain is about 100x.
     
  10. clbeav

    Thread Starter New Member

    Jan 28, 2011
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    The main problem about that circuit is my other spec that I failed to mention. When negative feedback is added to reduce to voltage gain to about 50, then the bandwith doesn't stretch past 2MHz. That's the main problem I have now.
     
  11. clbeav

    Thread Starter New Member

    Jan 28, 2011
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    Btw, I changed the values to 1M and 300k back for the input last night when finishing the design. I must say my design looked pretty close to yours as my Rd was almost 4k with Rs at 300.
     
  12. t_n_k

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    Mar 6, 2009
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    Hence my earlier comment about providing forum members with a complete picture of what you are trying to achieve.

    The expectation is that negative feedback generally increases bandwidth. If the overall gain requirement is reduced to 50x (rather than 100x) I would expect it would be possible to achieve the 2MHz (or better ~2.5MHz) bandwidth target.
     
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