Help with combination lock circuit

Discussion in 'General Electronics Chat' started by amruth11, Nov 17, 2011.

  1. amruth11

    Thread Starter Member

    May 24, 2011
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  2. MrChips

    Moderator

    Oct 2, 2009
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    The 4081 chip is a quad 2-input AND gate meaning that there are four 2-input gates in the one package. Only three gates are used in this project. The fourth gate is not used but the inputs need to be connected, in this case to Vss (GND). The gate in the upper right of the schematic is simply indicating how the unused gate is to be connected. This is correct and is the standard professional practice.
     
  3. amruth11

    Thread Starter Member

    May 24, 2011
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    So, it means that it has nothing to do with the circuit but it just shows how it supposed to be connected if used. If i am wrong plz help me out by explaining it cause i am not a pro.
     
  4. MrChips

    Moderator

    Oct 2, 2009
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    Not quite.

    ... it just shows how it supposed to be connected if NOT used.
     
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  5. cube01

    New Member

    Mar 10, 2011
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    The first part (left hand part) is saying that pin 7 of IC1, IC2, and IC3 go to Vss, and pin 14 of those ICs goes to Vdd...

    The second part (right hand part) is saying, that for IC3, you need to short pins 12 and 13 together and connect them to Vss. This is necessary, like Mr Chips said, because that gate of the IC is not being used (since that IC is a quad gate, and you are only using three of them.)

    You may already know this, but just in case - IC1A and IC1B are the same physical "chip". As are IC2A and IC2B. And also as are IC3A, IC3B, IC3C, and IC3D.... IC3D being the unused gate of the physical "chip" that is the 4081N.


    Hope that helps...
     
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  6. amruth11

    Thread Starter Member

    May 24, 2011
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    Thx for the help guys, now i can carry on the project. :)
     
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