For part of an exam tomorrow i need to build a 3 bit asynchronous counter that counts from 1 to 6 and uses d flip flops with positive edge trigger and active low set and reset. I think i can build the d flip flop counter, but how do i make it so it goes from 1 to 6, and leaves out 000 and 111?

 

I'm guessing you know you will need 3 D flip-flops. Write the excitation table (given current and next flip-flop states) for each of the D inputs and reduce to minimum logic using a minimization method of your choice. Implement the minimized logic using gate types of your (or the examiner's) choice.