Help with a differential amplifier small signal model

Discussion in 'Homework Help' started by HunterDX77M, Apr 27, 2012.

  1. HunterDX77M

    Thread Starter Active Member

    Sep 28, 2011
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    Hey Guys,

    In the attached circuit, if v1 = v2 = 0 is it safe to say that the circuit is symmetrical and that IQ splits evenly between the two transistors?

    Then when going to the small signal model, if I open IQ, does the third transistor fall out of the circuit, leaving only the first and second?

    To get the values of the resistors, I was told to solve them under the following conditions:
    * v1 = v2 = 0,
    * Vo = 0
    * IC3 = 0.4 mA
    The resistors turned out to be RC1 = 3.684 kΩ and RC2 = 7.5 kΩ

    Please don't hesitate to ask for further information if necessary.
     
  2. WBahn

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    Mar 31, 2012
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    Technically no, because the emitter loads are not identical. But as long as the base current in Q3 is small compared to the current source, it is a reasonable (and usual) assumption to make. Just be sure that if you are designing such a circuit, that you make sure that this condition is satisfied.

    No, you replace the transistors (all three) with their small signal equivalents.


    Your RC2 is correct, but the value of RC1 is going to be determined by the current source value, which you haven't supplied (or, if you have, I missed it). The analysis you are doing here is NOT small-signal, you are working with the DC bias conditions of the circuit.

    Consider the following:

    1) What is the emitter voltage of Q3?
    2) What is the base voltage of Q3?
    3) What does the collector voltage of Q2 need to be?
    4) What is the voltage across RC1?
    5) What is the current in RC1?
    6) What does the resistance of RC1 need to be?
     
  3. t_n_k

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    Did you mean (Q1 & Q2) collector loads?
     
  4. HunterDX77M

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    Sep 28, 2011
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    Oops, sorry. IQ is 0.5 mA.
     
  5. t_n_k

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    Were you given β(DC) values for Q1-3?
     
  6. WBahn

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    Uh. Oops. Yeah. My bad.
     
  7. WBahn

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    In that case, your answer for RC1 is in the ballpark, though if you assume a base-emitter voltage of 0.7V and a beta of 100, then it works out about right.
     
  8. HunterDX77M

    Thread Starter Active Member

    Sep 28, 2011
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    Yes, I was told to assume the VBE drop of 0.7 V. The β values are 120 for the two PNP's and 180 for the NPN.
     
  9. HunterDX77M

    Thread Starter Active Member

    Sep 28, 2011
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    I'm still having some trouble with understanding how active loads work. Does anyone know a good resource online that can explain it clearly?
     
  10. Jony130

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    Feb 17, 2009
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    I don't see any active load in your diagram.
    For me we have a active load when we use a constant-current source instead of Rc resistors.
     
  11. HunterDX77M

    Thread Starter Active Member

    Sep 28, 2011
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    Could someone confirm that the attached image is the correct small signal model? If it is correct, is there a glaringly obvious way to simplify the circuit? Thank you!
     
    Last edited: Apr 28, 2012
  12. Jony130

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    The small signal model look OK.
    I don't see any errors.
     
    HunterDX77M likes this.
  13. WBahn

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    As Jony130 says, an active load requires an active component in the load, which this circuit doesn't have. But the basic idea is the same as a passive load. Your amplifier transistors try to change the current flowing in the load and the load tries to keep the current in it the same. So one of two things (or some combination of both) must happen, either the transistor must establish a voltage at the junction of the collector and the load that forces the current in the load to change or the load must establish a voltage at that same junction that forces the transistor to stop trying to establish the different current. In practice, a combination of the two happens and a voltage is established at that junction that results in the same current in both the load and the transistor that is consistent with the I-V characteristics of both devices (if done graphically, this is known as a load-line analysis).

    It might help to point out that in order for an amplifier to work with an active load, either the load or the transistor has to be treated as a non-ideal current source. If they are both ideal current sources, then there is no mathematical solution (even if the currents in both are perfectly matched). Fortunately, we don't live in an ideal world and neither is ideal in practice.
     
  14. t_n_k

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    Since you calculated RC1 to three decimal places I thought I should "nitpick" on the RC1 value.

    Q3 collector current is 0.4mA. With Q3 β=180 this gives Q3 IB=2.222uA and IE=402.222uA. With the RE=0.5kΩ the emitter resistor voltage drop is 0.2011V. Hence with Q3 VBE=0.7V the drop across Q2 RC1 is 0.9011V.

    With the current source of 0.5mA and Q1 & Q2 matched, the Q2 emitter current is 0.25mA. With Q2 β=120 the Q2 base current is 2.066uA making the Q2 collector current 247.9uA. The Q2 RC1 current is then Q2 collector current minus Q3 base current or 247.9uA-2.222uA=245.7uA. With a drop of 0.9011V across Q2 RC1 this means RC1=0.9011V/245.7uA=3.667kΩ

    My (albeit manifestly ludicrous) point being if you are going to quote a value to three decimal places you should have a sound justification.
     
  15. WBahn

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    I definitely agree with t_n_k, though I chose not to bring it up given how many other people post every digit their calculator spews out, which is sometimes more than 32 digits.

    It's fine to carry the extra digits when doing the math (in fact, you should carry a couple to prevent inadvertent roundoff errors), but should report the final answer only to the degree that is justified. Ideally, this would involve performing a propagation of errors analysis, but in most engineering fields it is considered acceptable to simply report 3 sig figs unless something really justifies more (or less). Keep in mind that using 1% resistors (which are generally considered "precision" resistors) limits you to two sig figs, so reporting to three is usually the most you can claim is reasonable.
     
  16. HunterDX77M

    Thread Starter Active Member

    Sep 28, 2011
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    I'll keep that in mind for next time, thanks. :)

    By the way, does anyone other than Jony130 think that my small signal model is correct?
     
  17. t_n_k

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    I agree with Jony130.
     
  18. WBahn

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    I agree with t_n_k's agreement with Jony130.

    In general (no guarantee, though), if Jony130 had said it was correct and if someone disagreed with that, then they would have said so. I certainly looked it over but chose not to post because Jony130 had already said what I would have said. I Imagine t_n_k did the same thing. But, of course, you have no way of knowing that.
     
  19. HunterDX77M

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    Sep 28, 2011
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    Thanks all. I guess all that remains is the analysis. Oh what fun that'll be . . .
     
  20. Jony130

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    For this simple circuit we can find voltage gain without analysis the small-signal model. All we need to do is to treat each of the stages of a amplifier separately.
    The first stage is differential amplifier. The voltage gain for this stage with asymmetric output is equal to:

    Av1 = Vin/Vo1 = Rc1/ 2re

    But in our case the differential stage is also load by Q3 input impedance.
    So the voltage gain will be smaller

    Av1 = Vin/Vo1= ( Rc1|| RinQ3 ) / (2re)

    Q3 work as a CE amplifier so the input impedance is equal to :

    RinQ3 = (β3 + 1) * ( re3 + Re)

    The second stage work as a common emitter (CE) stage.
    As you should know the voltage gain of this stage is equal to:

    Av2 = Vo2/Vo1 = Rc/ ( re3 + Re)

    And the gain of the whole amplifier is equal

    Av = Av1 * Av2 = ( Rc1|| RinQ3 ) / (2re) * Rc/ ( re3 + Re) ≈ 225.915V/V

    I hope that I don't do any stupid mistake in my analysis. And now I'm waiting for your result.
     
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