# Help with a bjt common emitter amplifier

Discussion in 'Homework Help' started by albertino, Apr 9, 2008.

1. ### albertino Thread Starter New Member

Apr 9, 2008
5
0
Hi everyone,
This is my first post on this forum.
I'm stuck on an exercise with a common emitter amplifier...
Is it possible to ask here a possible solution?

Thanks...

2. ### rwmoekoe Active Member

Mar 1, 2007
172
0
shoot it out, man

May 16, 2005
5,072
6

4. ### albertino Thread Starter New Member

Apr 9, 2008
5
0
Ok guys, thank you very much...
I'm writing down all the calculations done so far and the circuit with the questions...when ready I'll post it...

Sorry for my english...probably you have noticed that I'm not english but I'm trying my best...

5. ### David Bridgen Senior Member

Feb 10, 2005
278
0
Your English is fine albertino. It is far better than many of my fellow, English, countrymen.

6. ### hgmjr Moderator

Jan 28, 2005
9,030
214
I agree with David Bridgen, your writing is quite precise. If you had not mentioned that English was not your first language I am not sure that I could have figured it out from your post.

hgmjr

7. ### albertino Thread Starter New Member

Apr 9, 2008
5
0
Ok...
I have attached a doc file with two images.
The first image is the amplifier in a common emitter configuration.
The second image should be the answer of the 1st and 2nd question.

The questions of this exercise are:

1 Using the output characteristics provided, construct the dc load line, (show all the calculations). State why it is possible to assume the load does not affect its performance.​
2 Determine the output variations in VCE and IC for a signal input of 20sin(wt) uA. ​
Hence determine the current gain of the amplifier
3 Calculate the power dissipation and efficiency under these conditions. ​
4 Calculate the maximum efficiency of the amplifier.​
5 Determine a value of bypass capacitor which could be used for amplifying ultrasonic signals between 50kHz and 100kHz.​

1) Just following another exercise given during my classes I have tried to solve the first question as follow:

Step 1 KVL for output circuit
Vcc = Vrc + Vce + Vre
Vcc = Vre + Vrc + Vce
= Ic(Re+Rc) + Vce
Step 2 and 3
Set Ic = 0 => Vce = Vcc Vcc = 10V then plot the Vce point on the graph
Set Vce = 0 => Ic = Vcc / (Re + Rc) => 10V / (166Ω+500Ω) => 10V / (666Ω) => 0,015A => 15mA
Plot this point on the graph
These should be the points to plot the dc load line.
Why it is possible to assume the load does not affect its performance????
2) The second question is on the second image.
I think to have plotted correctly the 20sin(wt)uA input and calculated the
variations of Vce and Ic as well.
To calculate these variations I also needed to find the Q point on the dc load line.
These are my calculations to find the Q point:

Calculate Vb​
Vb = (Vcc * R2) / (R2+R1) = (10V * 33KΩ) / (33KΩ + 100KΩ) = (10V * 33000Ω) / (33000Ω + 100000Ω)
= (330000) / ( 133000) = 2,48V
Calculate Ve
Ve = Vb  0,7V = 2,48V  0,7V = 1,78V
Calculate Ie
Ie = Ve / Re => 1,78V / 166Ω => 0,010A => 10mA (≈Icq) ​
From the graph, we can see that Vceq = 3,4V

Current gain of the amplifier: ​
Current Gain = β= Ic/Ib At Q point, substitute Ibq and Icq
Icq = 10mA and Ibq ≈ 55uA
Icq = 0,01 and Ibq ≈ 0,000055
β= (0,01)/(0,000055) = 181
I hope is ok...
3)

Dc power dissipation (at Q point)

From graph, Vceq = 3,4V and Icq = 10mA

Pd = Vceq * Icq = 3,4V * 0,010A = 0,034W = 34mW

For the efficiency:

Caculate output power
From graph,

pk means peak to peak.

Vce (pk) = 2V and Vce(rms) = 4,5 / √2 V
Ic(pk) = 13mA and Ic(rms) = 2 * 10-3 / √2 A
Output power = Vce(rms) * Ic(rms) = (4,5 / √2 V) * (2 * 10 -3 / √2 A) = 4,45mW

Efficiency (η) = 4,45mW / 34mW = 0,13 or 13%

I'm stuck on the 4th and 5th question.
Can you see if what I have done so far is right and try to solve the
last two questions.

Thank you very much indeed.

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8. ### rwmoekoe Active Member

Mar 1, 2007
172
0
1). You’ve plotted the dc load line. As to why the load doesn’t affect the performance, it is because the load’s impedance (100k) is far too high compared to the rc (500). What again is that by asuming the load is resistive, the presence of load is only affecting the ac gain by a very small fraction, and the gain remains linear, as the load is calculated parallel to the R3 as Rc.
2). I think you’ve done good for DC signals. For AC signals, it is mentioned in the next point.
3). Up to the power dissipation, I think it’s right, for DC state.
For ac signal, remember that C2 is there, and it’s making the Re becoming around only 2.5 ohms at room temperature, 10mA quiescent Ie.
The next calculations should be based on this AC Re to be valid. (Ic rms, hence Vce rms). Your above calculations is true, though, for DC signals.
4). The maximum efficiency I think is achieved when the signal is occupying the whole range of voltage swing that the transistor is capable of with this configuration.
5). The value for the capacitors should be found at an impedance that gives –3db cut-off at 50kHz. You know, the formula r=1/(ωc).

Well, I could be wrong.