hi this is my first post here, i've been lurking for a few months. I need help with a logic implementation

The problem says to find the non-standard form with the minimal number of operators fuction is:

F = x'zw+xz'w+z'y'z'w'+xy'zw

I used a kmap to see how it would look, but noticed there are 2 ways of doing it i believe, if the function could be different but with this function. I got :

F = xw(z'+y')+X'(zw+y'z'w')

this is the right answer from a solution i have BUT i fail to see how it becomes 9 operators.

WHen i count these i get 3 OR's, 4 AND's, 6 NOT's. I know i am doing something wrong but my book does not explain any further when it comes to figuring out how many operators. I tried doing the implementations but do not see how they get 9 operators.

See the attachments.

 

You must first have in mind some implementation hints:
F=xw(z'+y')+x'(zw+y'z'w')
=xw(zy)'+x'(zw+(y+z+w)')

We are thus using one NAND gate ((zy)') and one NOR gate ((y+z+w)') to reduce the NOT gates. In total we have:
1 NOT
2 2-input AND
1 3-input AND
1 2-input NAND
1 3-input NOR
2 2-input OR
SUM=8 gates

So, um... yes... 8 gates. Why not?

But this is not the best solution by a long shot, because those gates come in IC's in packs of 4 or 3. If you use one 3-input AND, you must bring another two along, so you are better off with more gates but of the same type.

 

ohh wow thank you so much. I see its with de morgan's theorem that should have been obvious, I've been breaking my head with this all day. It all makes sense now. Thank you.

 

i think the schematic looks like this:

 

You must first have in mind some implementation hints:
F=xw(z'+y')+x'(zw+y'z'w')
=xw(zy)'+x'(zw+(y+z+w)')

We are thus using one NAND gate ((zy)') and one NOR gate ((y+z+w)') to reduce the NOT gates. In total we have:
1 NOT
2 2-input AND
1 3-input AND
1 2-input NAND
1 3-input NOR
2 2-input OR
SUM=8 gates

So, um... yes... 8 gates. Why not?

But this is not the best solution by a long shot, because those gates come in IC's in packs of 4 or 3. If you use one 3-input AND, you must bring another two along, so you are better off with more gates but of the same type.

sorry i just realized they actually want 9 operators. currently trying to find how to get it there.

 

I noticed that you wanted 9 operators, but I though a better solution would be more acceptable.
There's no reason you would want to do it with 9, apart from some professor's inexplicable fixations.

You can always separate the 3-input AND to get the result you want. Can you guess what will you break it into?

 

This might be a solution ....

 

It may well be the case that the function

F = x'zw+xz'w+z'y'z'w'+xy'zw

cannot be minimised further than

F=wx'z+wxz'+w'y'z'+wy'z

for the SOP form.

I'd be interested to find out.

 

cannot be minimised further than

F=wx'z+wxz'+w'y'z'+wy'z

for the SOP form.

I'd be interested to find out.

My Karnaugh Map draws the same conclusion.

 

This SOP form needs 4 NOT gates and 5 3-input NAND gates to be implemented. 9 gates in 3 IC's in total.

The solution I suggested in post #2 needs 8 gates but 6 IC's.

Guess which is better?

 

Hi Georacer,

Did you check that the original

F = x'zw+xz'w+z'y'z'w'+xy'zw posted by Damp48

and the subsequent

F=xw(z'+y')+x'(zw+y'z'w') you posted [as per Damp48's reduction]

are logically equivalent?

I'm not sure they are.

 

Blimey, when will I learn?

Ok, OP, please tell us whether the solution of your book is wrong or you did a typo.