HELP: serial communication between two 7495s

Discussion in 'The Projects Forum' started by glitterized_dreamz, Mar 10, 2007.

  1. glitterized_dreamz

    Thread Starter New Member

    Feb 13, 2007
    6
    0
    Hi,

    I’m currently brain storming for a project that will use two 7495s (4-bit parallel-in serial-out) to perform serial communication. The first one will take parallel-in, serial-out…the second one will take that serial-in, and display parallel-out. For reference of the chip, visit

    http://www.ee.washington.edu/stores/DataSheets/74ls/74ls95.pdf

    Being new to all this stuff, I am very unsure how to do this project, but I’ve come up with a couple or ideas and questions regarding this project, please feel free to correct any misconceptions and fill in the blanks…cause I sure could use the help.

    Question 1:
    Is there some trick to converting parallel input to serial output, and vice versa? Or am I correct in the following observations?

    Register # 1 (parallel-in: serial-out)

    The first thing that comes to mind is that S (the mode) would have to be 1 to take in the parallel input…but the output will also read parallel. I could switch S to 0 to shift the bits out, however the bits will be read backwards.

    Question 2:
    Should I shift left to get the correct result? According to my notes, in order to shift left, I have to rewire Q3 to P2, Q2 to P1, and Q1 to P0.

    Question 3:
    It also states you should be in parallel mode to shift left…wouldn’t this interfere with the original parallel input?

    Register # 2 (serial-in: parallel-out)

    In this register the mode S will be 0 (serial-in), and the input will come from Q0 (if bits are shifted left).

    Question 4:
    Once all 4-bits are in their appropriate places, do I just set S to 1 to read the parallel output?

    Question 5:
    There are two clocks to each 4-bit register, why are two clocks needed? I know there is one assigned to each mode, but I don’t understand why they would need different signals.
    I DO know there is an inversion needed between the clock cycles for register 1 and register 2. But what relationship should the clock signals (within the same register) have?
     
  2. thingmaker3

    Retired Moderator

    May 16, 2005
    5,072
    6
    Answer 1: Your assessment is correct.

    Answer 2: And operate in parallel mode - you basically load a hardwire shift of the output into the input.

    Answer 3: This would only interfere if you had no external gating to select between shift and load. No chip is an island. ;)

    Answer 4: No action is needed to read the output. The output is always there.

    Answer 5: Look at the Mode Select Truth Table on page two of the datasheet. The falling edge of CP1 causes right-shifting if S is low. The falling edge of CP2 causes parallel loading if S is high. Most applications would call for parallel loading at CP2 frequency, shifting out of Q3 along a data line and into the second chip's Ds at CP1 frequency, and then reading the second chip's o/p.

    Read, load,
    wait, shift,
    wait, wait,
    wait, shift,
    wait, wait,
    wait, shift,
    wait, wait,
    wait, shift,
    repeat.

    Reading, of coure, would meant gating the Q o/p's of the second chip after having shifted all the bits in. Again, no chip is an island. ;)
     
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