Help reqd for this schematic of digital clock using 8085 up

Discussion in 'The Projects Forum' started by Anirban, Apr 29, 2011.

  1. Anirban

    Thread Starter New Member

    Apr 29, 2011
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    Hey all. I m new to this forum. I m making a digital clock using 8085 up. I have attached my schematics. However i wanted to make sure if this schematic is completely right (acc to me it is). Any suggestion is thoroughly welcomed.
     
  2. t06afre

    AAC Fanatic!

    May 11, 2009
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    Can you post your schematic as pdf or png file. I can not open it...
     
  3. Anirban

    Thread Starter New Member

    Apr 29, 2011
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    ya sure. I have attached the two image files
     
  4. t06afre

    AAC Fanatic!

    May 11, 2009
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    I see some problems
    On IC3 that is the ROM circuit. The unused adress line should be tied low. Never leave inputs on digital logic floating.
    The system has no RAM as I can see. It that correct?
    are you using a buffer(s) on both the data and adress bus (all used lines). A typical buffer for the data bus is some kind of 74x245 circuit.
    I must add I never worked with the 8085 circuit, but did work on the Z80.
     
  5. Anirban

    Thread Starter New Member

    Apr 29, 2011
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    well yes, i have left the unused address pins(A13 and A14) open on purpose. If i dont connect them to low, it shouldnt be a prob ( ghost addressing.)
    secondly, RAM is present inside the 8155 chip which is large enough for my purpose.
    Thirdly, i have used a latch to decode the lower order address bits from the address/data bus but i have not used any buffer as such.
    What can be the prob if i dnt use buffer with the address/data buses?
     
  6. t06afre

    AAC Fanatic!

    May 11, 2009
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    The problem not buffering is that the external circuits may draw more current than the 8085 can source(or sink). As I remember the 8085 has poor driver capabilities. Another thing that is more bad design is the floating address bus pins on the ROM chip. The fact is that they will probably take high level. But it is no guaranty for that. Due to stray signal they may in worst case take high or low level in a random way. Very hard to debug.
     
  7. t06afre

    AAC Fanatic!

    May 11, 2009
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    If I was you I would also have simplified the design quite a lot. By memory-mapping all external devices. Or at least the the 8155. As it could be awkward to program your system with all the memory in IO area. Your system configuration will allow for putting all IO devices in the memory area.
     
  8. archiesweet29

    New Member

    Feb 7, 2012
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    HI,,Anirban........ have u got the correct schematic of 8085up digital clock manager.??? can u please attach it here
     
  9. n1ist

    Active Member

    Mar 8, 2009
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    A few notes:
    - The schematic is very hard to read; rather than drawing each chip or subsection separately, it is sometimes better to show the interconnections on related parts. For example, in the LED section, showing at least the display, current limiting resistors, and digit select transistors wired up would make it easier to follow
    - Right now, the schematic is very wide and requires much moving around to see it.
    - Use meaningful net names - digit select should be dig1 - dig4 (DP is usually reserved for decimal points), segments should be seg_ - seg_g (1 - 10 are poor net names as they can easily be confused with pin numbers)
    - It would be nice to see resistor values in the schematic
    - Double check the values on your reset circuit; 100n is more common than 22p here
    - The wiring on PC0/PC1 for the pushbuttons is wrong
    - There are quite a few text collisions (net names, parts values, ref des overlapping each other or wires)
    - 7805 regulators need 100n on both Vin and Vout to gnd to avoid oscillations
    - I would add grounds to all of the expansion headers

    /mike
     
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