Help proofing this timer before build..

Discussion in 'The Projects Forum' started by triggernum5, Feb 1, 2009.

  1. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    I adapted this from a circuit I found a long time ago.. The idea is a relay timer that can be adjusted period-wise since the vast majority of cheap timers on the market are locked in to 24hr cycles..
    Operation: ICs 1&2 and adjacent pieces multiply the xtal clock to produce 0.5s, then 60s periods..
    ICs 4&5 simply count minutes and reset themselves (and the flip-flop) once every day period.. (Note, in the circuit, these chips are currently wired for 24hr (1440min) days..
    ICs 6&7 are to be set with the number of delay minutes before resetting ICs 4&5 respectively.. Once ICs 6&7 set/reset the flipflop during the initial cycle they sit dormant, and IC's 4&5 will be sync'd to repeat each day period, IC4 turns it on, IC5 turns it off.. (Note ICs 6&7 are also wired for 24hr.. This is nonsensical for their purpose obviously, but I was cutting/pasting images..)
    The battery is only there to keep the count timing in the case of an outage

    For example, lets say ICs 4&5 are each set for 1080 minutes (an 18hr day), IC6 wired for 60min, and IC7 wired for 120min.. When the circuit is started, it will count 60minutes then IC6 will reset/sync IC4 turning on the relay.. 60minutes after that, IC7 will reset/sync IC5, turning off the relay.. ICs 4&5 will continue this operation each day since they will each do their switching job every 1080 minutes..

    So anybody notice any glaring stupidity??
     
    Last edited: Feb 1, 2009
  2. Wendy

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    Mar 24, 2008
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    Just a suggestion, don't post schematics that big, they screw up that and all following posts on the thread, making the text hard to read. Also, .jpg blurs everything as part of its compression, use .gif or .png instead.
     
  3. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    Didn't even realize it was that big.. I hate that too.. Editting down to the thumbnail now.. I didn't exactly have an unblurred copy to start with, but I think anything pertinent is readable.. If ppl have problems reading it I guess I could redraw it from scratch and keep it as losless as possible..
    IC1 - CD4060B (counter)
    ICs 2,4,5,6,7 - CD 4040B (counter)
    IC3 - CD4013B (flip-flop)
     
    Last edited: Feb 1, 2009
  4. Wendy

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    Mar 24, 2008
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    I'll study it more later, but nothing jumps out. I'm having some problem reading the text, but so far I think I've muddled through.
     
  5. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    I improved the readability a bit, and altered the period/delay setting circuitry to be adjustable.. The chips are labeled across from MSB to LSB, and can be jumpered to set minutes in binary.. ICs 4&5 should both be set to the desired amount of minutes in a day/cycle period.. IC6 is set to the delay in minutes from circuit powerup to when relay comes on, IC7 set to the delay from circuit powerup to when the relay goes off.. (eg IC7 is set in minutes to what IC6 is set to plus the number of minutes the relay is to be on..) (Or vice versa if you want the powerdown signal to come before the powerup signal..) Just don't set ICs 6&7 to the same value, or you'll bug out the logic..
     
  6. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    Will I need diodes at pins 1&2 of IC3, and the outputs of ICs 6&7 to prevent them from sinking current destined for the reset pins of ICs 4&5?
     
  7. Wendy

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    Mar 24, 2008
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    If IC3A notQ is high, won't it short out on IC7 if any of its pins are low? I see what you're trying for, a massive AND gate, but you have two outputs tied together on a logic family that doesn't allow for it. Same thing for IC6.
     
  8. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    Well it just occured to me that ICs 6&7 will not be reset, therefore they would have ANDed high output any time when counters 4&5 will be reset.. I think Q & notQ might sink the outputs of ICs 6&7 away from resetting ICs 4&5 respectively, and flipping the IC3B flip-flop if I don't add fb diodes coming out of Q and notQ on IC3A..
    I'm thinking Q/notQ may sink the current the same way the low counter outputs do..
     
  9. Wendy

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    Mar 24, 2008
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    If it is CMOS it sinks current, think pull up AND pull down transistors. I could be wrong, but if the U3 Qs are high the diode is a direct short through to IC6 or IC7 low.

    CD4013 Datasheet

    CD4060 Datasheet

    I don't see anything in the datasheets that would say otherwise. CMOS outputs are pretty simple that way.
     
  10. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    But I can just tack in diodes like a mad fiend, and no harm, no foul right??
     
  11. Wendy

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    Mar 24, 2008
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    Are you meaning to OR the outputs together? If so think about using a gate. If you use a lot of diodes then the diodes might as well not be there.

    The problem with diode gates is there needs to be a buffer now and again.
     
    Last edited: Feb 1, 2009
  12. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    I don't get what you mean by ORing.. Well I mean I know what ORing is, I just don't know which pins you mean..
    I added the diodes out of IC3, and I realized I needed caps out of ICs 6&7 to prevent 11 getting applied to flip-flop B.. (You may have mentioned that earlier, but the thought just sank in..)
    Something seems off though.. Here is a schematic of the original concept as well.. In that, ICs 6&7 didn't exist, but rather normally closed dead-man switches were put in so you could manually reset ICs 4&5 at the desired time on the first cycle of operation, and it repeats that activity each cycle afterwards..
     
  13. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    Heres what I was thinking with the 555's, but it seems overcomplicated.. The 555 pulse would be extremely short, I haven't done calculations yet..
     
  14. Wendy

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    Mar 24, 2008
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    Why do you need a monostable?

    About the ORing of the outputs, many TTLs will allow for it, but you need a pullup resistor. CMOS is pretty simple, if you want to tie to outputs together directly bad things happen.
     
  15. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    Well the tie up details I'll look into next.. The original circuit used that concept, and chose the chips to do it with.. I'll worry about the function of the original concept after I work out my alteration logic..
    The 555 is in monostable because every time it pulses it will force reset IC 4 or 5, (whichever one that 555 is tied to reset).. Aside from a single forced reset that only happens for each IC 4 & 5 on the very first day cycle, they will only reset when their day count completes.. Astable pulses would constantly reset the day counters rendering everything useless.. A permanently high output going into the pnp bases would prevent ICs 4 & 5 from ever starting..
    Again what happens with this circuit as an example.. Lets say you want the relay to come on once/hr for 10min, and you want the first on period to start 5 minutes after you plug it in.. A total cycle is 1hr, so:
    ICs 4&5 get jumpered to count to 60 before auto-resetting..
    IC6 gets jumper set to 5
    IC7 gets jumper set to 15 (delay_before_powerup + run_time)
    When its plugged in, all minute counters start counting..
    At 5 minutes IC6 starts the 555 which resets IC4 to zero and turns on relay..
    (From this point on, IC6, and its 555 are irrelevant to the circuit aside from sinking current.. IC4 will independantly turn on the relay every 60min..)
    When IC7 hits its count of 15 ten minutes later it pulses its 555 to reset the count of IC5 to zero and turn off the relay..
    Now IC7 and its 555 have completed their job, and IC5 will auto-reset and kill the relay every 60 minutes, 10 minutes after IC4 turned it on..
     
  16. triggernum5

    Thread Starter Active Member

    May 4, 2008
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    I redrew the schematic..
     
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