Discussion in 'Homework Help' started by PauAgGiron, Oct 27, 2014.

1. ### PauAgGiron Thread Starter New Member

Oct 27, 2014
8
1
Analyze the network shown in the Figure below and design a gate network using AND, OR, XOR, and NOR gates that implements the same function. (Hint: z=1 if the inputs to the decoder and the multiplexer are identical).

2. ### shteii01 AAC Fanatic!

Feb 19, 2010
3,387
497
"zero input produces zero output"

Where is your input to the solution of this problem?

3. ### tshuck Well-Known Member

Oct 18, 2012
3,531
675
...you first. This is Homework Help, remember. We will help, you must put in the work and show it.

4. ### PauAgGiron Thread Starter New Member

Oct 27, 2014
8
1
I don't even know where to start. How do you convert those blocks into gates? Should I start by doing some truth tables?

5. ### WBahn Moderator

Mar 31, 2012
17,743
4,795
What? Is this a homework problem that you are assigning to us?

You need to show YOUR efforts to solve YOUR homework. Then we can see where you are going right and wrong and help YOU move closer to a solution.

Take your best shot. In particular, see if you can leverage the hint to significantly reduce the complexity of the problem. It's actually pretty easy if you break it up into two smaller problems, but it is pretty daunting if you try to tackle it all at once since you have eight inputs and, hence, 256 rows in your brute force truth table.

PauAgGiron likes this.
6. ### PauAgGiron Thread Starter New Member

Oct 27, 2014
8
1
Thank you! I am going to read the chapter again and come back when I have some progress.

7. ### WBahn Moderator

Mar 31, 2012
17,743
4,795
If that is truly the case, then a good place to start would be getting a drop slip and a change of major form. Otherwise, you need to start swinging, even if the swings aren't too good at first.

You could do that and it would technically meet the letter of the problem as given above. But you can do it in far, far fewer gates than that.

Not blindly, since you will have a 256 entry table and doing K-maps (if you know about them yet) on eight variables is NOT fun (six is the usual limit for doing them by hand).

Look at my prior post and see if that gets you started.

8. ### MrCarlos Active Member

Jan 2, 2010
400
134
Hello PauAgGiron

If you try to develop each (MUX, Binary Decoder, MUX) box with AND, OR, XOR, and NOR will be very hard.

The box on the left is a: Selector-MUX.
You select, via the control inputs c and b, any data input: 0, 1, 2 or 3 which Will appear at its output W.

The box, in the center is a: Binary to octal decoder.
According to the binary code in their Control Inputs 0, 1, 2, it appears 1 (high level) at its outputs from 0 up to 7.

The box on the right is a: Selector-Mux.
You select via the control inputs h, g, f any data input from 0 to 7. which appears at its output Z.
Take a look at the documents attached to You. Especially the section entitled LOGIC DIAGRAM.
Looking at those pictures, you can discover how to develop your circuits with AND, OR, XOR, and NOR Gates.
You can find more of them in this link: http://www.alldatasheet.com/
You can inquire by part number or description.
.

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9. ### WBahn Moderator

Mar 31, 2012
17,743
4,795
Not that hard at all, just unnecessary. Both the multiplexers and the decoders are very simple, straightforward circuits.

For instance, the decoder can be implemented using one inverter on each input line to provide the complementary control signals and then one three-input NOR gate for each output with the input being either the straight or the complement of each control signal. The muxes can then be implemented using a decoder with each output going into a 2-input NAND along with one of the mux input signals and all of the outputs from the NANDs being NANDed together to give the final output. Not hard at all.

By focusing on the hint that is given, the decoder and the 8:1 mux can be replaced by just three 2-input XORs and a 3-input NOR gate. If I've thrown it together right, the rest of it can be done in one NOT, one 2-input XOR, and three 2-input NAND gates.