Help! Open collectors for ic

Discussion in 'General Electronics Chat' started by Robin Mitchell, Oct 31, 2009.

  1. Robin Mitchell

    Thread Starter Well-Known Member

    Oct 25, 2009
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    Hi everyone,

    My friend said that i needed my IC's (4000 series) to have open collectors or something so there wont be any short circuits. Now i have tried to research it and have gone as far as i can thrown a car!

    What are they, Why are they needed and how do i impliment them in my circuit!!!!

    Thanks :)
     
  2. hgmjr

    Moderator

    Jan 28, 2005
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    It would be helpful to know more about your application?

    hgmjr
     
  3. Robin Mitchell

    Thread Starter Well-Known Member

    Oct 25, 2009
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    Oh, i though you would know!!!

    My computer :)

    Its the outputs of the IC's.
     
    Last edited: Oct 31, 2009
  4. studiot

    AAC Fanatic!

    Nov 9, 2007
    5,005
    513
    Perhaps your friend should spend more time listening at school?

    4000 series are CMOS (or field effect transistor) based and do not have collectors.

    There are some open drain versions in this series.


    To be of any use the output transistors in the IC needs to have an electrical load.
    There are two possibilities;
    1) either the load is inside the IC or
    2) you have to provide it yourself.

    Case 2 is called open collector or open drain. In this case you connect your external load across (or between if you like) the output and supply.
     
  5. Robin Mitchell

    Thread Starter Well-Known Member

    Oct 25, 2009
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    errrrrm.... ?
    so the 4000 series can have there outputs connected to an other ic or load with no problem?
     
  6. studiot

    AAC Fanatic!

    Nov 9, 2007
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    Facetious remarks about science in general and other's posts in particular do not lead to understanding.

    You were asked about your application, it's your computer so if you want to find out how to connect it to something you will need to be more forthcoming.
     
  7. beenthere

    Retired Moderator

    Apr 20, 2004
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    For further information, open collector logic was developed so multiple gates could share the same line without causing failures in their output stages. The more recent logic uses so-called three state outputs, so the gate essentially becomes invisible (electrically) if an enable signal is not asserted.
     
  8. Papabravo

    Expert

    Feb 24, 2006
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    There are at least two traditional ways to create a bus where multiple outputs can be connected together.
    1. Open Collector(TTL case), and Open Drain(CMOS case)
    2. 3-State or Tri-state outputs
    In case 2. the rule that must be enforced is that you cannot have two outputs enabled at the same time. In this context, enabled means "able to drive the bus" to a logic `1' or a logic `0'. All other outputs must be in the high-impedance state.

    In case 1. the Open Collector or open drain outputs can only drive a logic `0' onto the bus because their Collectors(Drains) are not connected to anything inside the chip except the pad which is bonded to the pin on the IC. A HIGH or logic `1' is provided by a single external pullup resistor. Even if two outputs are active at the same time it does not hurt anything electrically. It is incorrect functionally for this to happen but at least it does not let the magic smoke out.

    In order to understand what is going on, look at a simple NPN transistor switch and eliminate the collector load resistor. This is what the open collector output stage looks like. Then imagine that a bunch of those transistor switch outputs are connected together. No problem yet, but also trivial in function. Now add a single pullup resistor to VCC for all of the outputs which were connected together.
     
  9. loosewire

    AAC Fanatic!

    Apr 25, 2008
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    Could you post a diagram to illistrate.
     
  10. CIRCUITPRO

    New Member

    Nov 21, 2009
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    The open collector devices also allow for a "wired or" circuit.
     
  11. Papabravo

    Expert

    Feb 24, 2006
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    A low OR a low OR ... is a low. A "so-called" negative logic OR; a positve logic AND. By DeMorgans rule: a high AND a high AND ... is a high.
     
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