I've been working on a switching power supply project, and one element of the design involves over voltage and reverse voltage protection. I thought I had that part sorted out (see this thread), but now that I've built a prototype that includes the OV/RV circuit on the same board with the SMPS, I have a really bizarre problem.

When the board is powered with no load on the output, it appears to behave normally and output is 5.19V, as it should be. However, when a load is placed on the output, the two 10μF input capacitors (MLCCs) emit a surprisingly loud piezo-like buzzing sound, and output drops to ~1.4V. Buzzing frequency drops as input voltage rises, and vice versa. If the OV/RV circuit is bypassed and input power is applied directly at the MLCCs, the SMPS works normally.

I went back to an earlier SMPS-only prototype board and connected a separate OV/RV test board to it via wires. Same problem.

I've tried paralleling additional capacitance with the MLCCs. Each step up in total capacitance seems to slightly decrease the volume of buzzing, increases input current draw, and increases output voltage. I ended up with MLCCs soldered in a comical five-high tower (total 126μF), but the problem remained, and output never got above ~3.2V.

Then I went all-in and soldered a 220μF electrolytic to the MLCC tower (total 346μF). Output rose to ~5V and the buzzing was very faint, but output voltage rose and fell randomly by ~100mV and input current varied by ~250mA. Again, this SMPS is rock solid -- and dead quiet -- without the OV/RV in circuit.

I'm attaching the core schematic, bill of materials, and a short audio recording of the MLCCs in full song. The recording starts with input voltage at 7V. Vin then increases slowly to ~18V, where the OV protection transistor cuts it off, then decreases back to 7V.

Oh, and one more thing. This problem seems to be causing the OV protection transistor to overheat. Either that, or I haven't spec'ed it adequately for the board's current demands (typically 14V at 0.9-1.8A). Here are some numbers on the transistor in-circuit (Vin=14.00V):

• 2x 10μF MLCCs, no load: Ie=15mA, Vce=5mV
• 2x 10μF MLCCs, 1.75Ω load: Ie=180mA, Vce=410mV
• 2x 10μF MLCCs + 220μF electrolytic, 1.75Ω load: Ie=1.45A, Vce=2.5V. Smoke within ~45 sec.

The latter two Vce numbers are way out of line from the data sheet.

This has me completely baffled. Does anyone have any idea what the problem could be? Let me know if any additional measurements would be useful.

Thanks.

 

I'm guessing you are designing based on Fig. 10 of the PNP's datasheet. These are typical values. Note that, with Ic=2A, the only guaranteed Vce(sat) spec is with Ib=40mA. Your Ib is <<40mA.
What I'm suggesting is that Q3 might be the problem, not just the victim of another problem.
A PMOS FET might be a better choice for Q3.

 

Ron,

Thanks for your reply. I didn't really "design" anything, as I'm a hobbyist rather than an engineer. I rely heavily on data sheet and application note examples, lots of trial and error, and help from kind folks like you!

The OV/RV circuit in this design is based on this Maxim note and this Hackaday post. I simply changed Q1 to carry more current, and changed Q2 to decrease package size and cost. My only other change was the Zener value.

If I understand you correctly, you don't think the PNP is turning on all the way, so it's oscillating, "choking" the current to the regulator, and the buzzing MLCCs are simply a symptom of this oscillation? Do you have any idea why this might be happening?

I've drawn a new schematic, substituting the AO3407A P-MOSFET (because I already use it for reverse voltage protection) for the PNP. Does the schematic look right?

Let me see if I understand how it works. Under normal operation, Q1 conducts because its gate is tied to ground through R3, while its source is at Vin. Q2 is off because its base and emitter are at the same potential. When Vin exceeds the Zener voltage, Q2's emitter goes higher than its base, turning Q2 on. This brings Q1's gate up to Vin, turning Q1 off. Does that sound right?

Just a few questions:

• Why would a MOSFET work better in this circuit than the PNP? I understand that the MOSFET will dissipate less heat, but why will it turn on and off more reliably?
• Is there a way to make Q1 -- whether PNP or MOSFET -- switch states "hard," so that it can't oscillate?

Thanks again.

 

Was it intentional that the MOSFETs are connected differently? In the Reverse Voltage Protection, the MOSFET is connected from Drain to Source and in the revised Overvoltage Protection, the MOSFET is connected from Source to Drain.

 

Was it intentional that the MOSFETs are connected differently? In the Reverse Voltage Protection, the MOSFET is connected from Drain to Source and in the revised Overvoltage Protection, the MOSFET is connected from Source to Drain.

It was. I'm no engineer, but I'll try to explain it as I understand it.

In the case of RV protection, if the FET were flipped (source to the left), it would still work under normal conditions, with the battery connected properly. But with a reversed battery, current could flow through the body diode, defeating the purpose of the FET. As configured, the body diode carries a tiny current for a tiny time, just to "bias up" the source relative to the gate, which turns on the FET. With battery reversed, gate and source are at the same potential, the FET is off, and the body diode cannot reverse-conduct.

In the case of the OV circuit, the FET has to be reversed (source to the left) to place its body diode in the right direction. If it were the other way around, the diode would still conduct during OV conditions, even if the FET were turned off. In fact, I think it would be impossible to turn the FET off!


Hope I'm not posting a load of garbage...

 

Ron,

Thanks for your reply. I didn't really "design" anything, as I'm a hobbyist rather than an engineer. I rely heavily on data sheet and application note examples, lots of trial and error, and help from kind folks like you!

The OV/RV circuit in this design is based on this Maxim note and this Hackaday post. I simply changed Q1 to carry more current, and changed Q2 to decrease package size and cost. My only other change was the Zener value.

If I understand you correctly, you don't think the PNP is turning on all the way, so it's oscillating, "choking" the current to the regulator, and the buzzing MLCCs are simply a symptom of this oscillation? Do you have any idea why this might be happening?

I've drawn a new schematic, substituting the AO3407A P-MOSFET (because I already use it for reverse voltage protection) for the PNP. Does the schematic look right?

Let me see if I understand how it works. Under normal operation, Q1 conducts because its gate is tied to ground through R3, while its source is at Vin. Q2 is off because its base and emitter are at the same potential. When Vin exceeds the Zener voltage, Q2's emitter goes higher than its base, turning Q2 on. This brings Q1's gate up to Vin, turning Q1 off. Does that sound right?

This is correct, except the MOSFET does not have an emitter. It is called the source.

Just a few questions:

• Why would a MOSFET work better in this circuit than the PNP? I understand that the MOSFET will dissipate less heat, but why will it turn on and off more reliably?
• Is there a way to make Q1 -- whether PNP or MOSFET -- switch states "hard," so that it can't oscillate?

Thanks again,

Eric

1) A PNP will come out of saturation if Ic/Ib > beta (Hfe). Beta is the transistor's current gain. It is much lower during saturation (Vce near 0V) than when Vce is a couple of volts or more. You want the transistor to stay saturated, to minimize power dissipation. Here is my guess at what's going on, and it's kinda tricky:
The switching regulator maintains constant output voltage, regardless of input voltage, while running at high efficiency. Let's say your PNP has inadequate base current to maintain saturation when Ic>1A. Now lets say that the load resistance is 5Ω. 5.19V/5Ω=1.04A. This causes Vce to increase, which reduces the input voltage to the swreg. It compensates by drawing more average current from the source (the PNP). This causes Vce to increase even more, starting a vicious circle which results in the swreg input voltage dropping to the point where it shuts down. Then the cycle repeats (oscillates). The PNP, of course, is getting hot, due to the increased current AND increased Vce.

MOSFETs don't draw any gate current except when switching (they do have gate capacitance), so the only change in Vds will be due to ΔIds*Rds. I don't think the circuit will oscillate with a PMOS replacing the PNP, but I can't guarantee it.

2) The overvoltage protection circuit could possibly be made to latch, with some hysteresis built in to reset it when the input voltage drops to an acceptable level. It would probably require an IC (comparator) as part of the circuit.

Question: What is your maximum load current on the output?
BTW, I would add another zener, to protect Vgs on the OV protection MOSFET. See the attachment, which is a sim of sweeping the input voltage from -20V to +20V.

 

Ron,

Wow, thanks! You've done a lot of work on this. Much appreciated.

Believe it or not, I think I almost understand your first point, re saturation of the PNP. When I adapted the Maxim app note circuit, the only things I changed were the transistors and Zener; I left the resistors as they were because I didn't realize their true purpose. I'm sure their values were selected to suit the FMMT718 transistors in the circuit, and they don't necessarily suit the devices I chose. That said, if inadequate Ib is the problem, couldn't we solve it simply by reducing the value of the 6k81 resistor below the base of the PNP? If so, how would I arrive at the right value? I presume a similar reassessment should be done for the control PNP, right?

Your sim result with the FET looks perfect! That may just be the solution.

I can test a lower resistor value with the board I have on the bench right now, if you think it might work. I'll can parallel another resistor (say, 2k?) with the 6k81 and see what happens.

I used a comparator to establish rising and falling enable thresholds for the regulator IC, so I had a feeling that might be the answer here as well. I'd rather avoid adding that complexity if I can.

Maximum load current from the SMPS is 4.2A.

Many thanks.

 

Ron,

Wow, thanks! You've done a lot of work on this. Much appreciated.

Believe it or not, I think I almost understand your first point, re saturation of the PNP. When I adapted the Maxim app note circuit, the only things I changed were the transistors and Zener; I left the resistors as they were because I didn't realize their true purpose. I'm sure their values were selected to suit the FMMT718 transistors in the circuit, and they don't necessarily suit the devices I chose. That said, if inadequate Ib is the problem, couldn't we solve it simply by reducing the value of the 6k81 resistor below the base of the PNP? If so, how would I arrive at the right value? I presume a similar reassessment should be done for the control PNP, right?

Your sim result with the FET looks perfect! That may just be the solution.

I can test a lower resistor value with the board I have on the bench right now, if you think it might work. I'll can parallel another resistor (say, 2k?) with the 6k81 and see what happens.

I used a comparator to establish rising and falling enable thresholds for the regulator IC, so I had a feeling that might be the answer here as well. I'd rather avoid adding that complexity if I can.

Maximum load current from the SMPS is 4.2A.

Many thanks,

Eric

The MOSFET you chose will get pretty hot. I estimate that, with Vin=7V, the current will be almost 4A (the current will go down as the voltage goes up). With max Rds(on) of about 60mΩ, this puts the max dissipation of each MOSFET at about close to a Watt. The simulation showed only about 0.55W each (sim models generally use typical specs). At 1W, you are at the upper limit of the absolute max dissipation, even with Tambient=25°C. I would choose a MOSFET with lower Rds(on).

I chose 7V as your minimum input voltage. If this number is higher, the dissipation will go down.

The PNP can handle more current. At Ic=4A, Ib needs to be >200mA to keep Vce(sat) acceptable. The problem with this is it wastes a lot of power. Furthermore, as the input voltage increases, the collector current decreases (due to the swreg characteristics). So, the base current could also be allowed to decrease, when in fact it will increase, if you use a simple resistor to provide base current. I don't think a PNP is a good solution for your power supply.

BTW, I used IRF7406 as the MOSFET in the sim, because I couldn't find a spice model for AO3407A. The devices have similar specs.

 

The MOSFET you chose will get pretty hot. I estimate that, with Vin=7V, the current will be almost 4A (the current will go down as the voltage goes up). With max Rds(on) of about 60mΩ, this puts the max dissipation of each MOSFET at about close to a Watt. The simulation showed only about 0.55W each (sim models generally use typical specs). At 1W, you are at the upper limit of the absolute max dissipation, even with Tambient=25°C. I would choose a MOSFET with lower Rds(on).

I chose 7V as your minimum input voltage. If this number is higher, the dissipation will go down.

I may have misled you WRT input voltage when I ran it from 7-to-18-to-7 when I recorded the buzzing caps. I just did that to emphasize the swing in buzzing frequency. In fact, minimum input is 10.5V and typical is ~14V. So, worst case dissipation in the MOSFETs would be around 400mW, assuming the SMPS is only 80% efficient.

Still, you have a good point. I'll peruse Digi-Key again and see if I can find a better Rds(on) in a similar package size and cost.

The PNP can handle more current. At Ic=4A, Ib needs to be >200mA to keep Vce(sat) acceptable. The problem with this is it wastes a lot of power. Furthermore, as the input voltage increases, the collector current decreases (due to the swreg characteristics). So, the base current could also be allowed to decrease, when in fact it will increase, if you use a simple resistor to provide base current. I don't think a PNP is a good solution for your power supply.

Hmmm, I see the problem. Wasting power wouldn't be an issue, as this isn't battery powered, but it sounds like keeping Ib "in the zone" is a tall order. I believe the Maxim note I copied from used this circuit to protect sensitive systems in a vehicle, so there wouldn't have been the same problems with widely varying current draw that I'm seeing with the SMPS.

I have a couple of the OV/RV test boards here. I'll rework one of them and see if I can dead-bug an AO3407A in place of the PNP. That should be a good eye test, if nothing else! I'll report back tomorrow afternoon.

What about the control PNP? Should I have any worry about it, given that I haven't optimized the 2k7 and 6k81 resistors feeding its base? How would I calculate proper values?

BTW, I used IRF7406 as the MOSFET in the sim, because I couldn't find a spice model for AO3407A. The devices have similar specs.

Close enough, I'm sure. Could you point me toward a source for this Spice simulator? I've heard of it, but never used it. It looks like a pretty handy tool.

Thank you again.

 

Ron,

I managed to get an SOT-23-3 MOSFET soldered onto the PNP's SC-89 footprint. It made a vast improvement, but still not perfect. The input caps no longer buzzed all the time with the SMPS under load, but they did buzz in a ~100mV window around the OV cutoff point, with Vin both rising and falling.

I remembered reading something in the description of a triac-based crowbar circuit about bypassing the triac's gate to ground with a small cap to ensure it switches hard and stays switched. I decided to try it here, bypassing the MOSFET's gate to ground.

First try was 0.1μF, and it helped some, reducing the volume of buzzing and narrowing the window in which it happened.

Next was 1.0μF. Again, slight improvement, but still a little buzzing.

Finally, I tried 4.7μF. From what I can tell by monitoring SMPS output with a multimeter, OV cutoff happens fast and sudden. I can only hear what sounds like a single, faint click from the input caps when Vin reaches OV cutoff (18.73V). There's a tiny bit of buzzing as Vin falls below OV cutoff (in a ~15mV window, just below 18.72V), but only if I strain to turn the fine adjustment knob on my bench supply as slowly as possible.

As an aside, I did try paralleling a 2k resistor with the 6k81 resistor on the base of the control PNP and the MOSFET (without the 4.7μF cap in place), but it had no effect. Bypassing the base of the control PNP with a cap to ground prevented the circuit from cutting off with Vin up to 20V.

So... If I assume that no system malfunction will produce an overvoltage that dwells at exactly 18.71-18.73V, and that any instance of overvoltage will be exceedingly rare and short-lived (both reasonable and safe assumptions, given that the main power supply should crowbar at ~16V), it seems that I have the problem solved.

New schematic attached. What do you think?


P.S. I'd still love to understand how the resistors were chosen at the base of the FMMT718 PNPs used in the original Maxim circuit, if you're able to offer any insight.

 

The control PNP and its associated resistors are pretty non-critical, so long as enough base drive is available for each one. I have no way of knowing what criteria the designer used to select them.
With the MOSFET in the OV circuit, you could make the gate resistor a lot larger (e.g., 100k).

 

Ron,

The control PNP and its associated resistors are pretty non-critical, so long as enough base drive is available for each one. I have no way of knowing what criteria the designer used to select them.

Thanks. No biggie; just curious.

With the MOSFET in the OV circuit, you could make the gate resistor a lot larger (e.g., 100k).

Got it... because a MOSFET gate "senses" voltage but doesn't flow current like the base of a transistor. There's no point bleeding current through a small resistor to ground. Good point.

-----

I'm a bit pig-headed about making things the best way I can, and I see this project as an opportunity to learn a lot about several kinds of circuits. That said, I've been mulling over this design and your comment about using a comparator to drive the MOSFET. First, I have three questions about the current design:

1. MOSFET Vgs(th) is -3V. This circuit will cut off Vin at 18V, but if Vin continued rising, the Gate Zener would create -3V Vgs once Vin exceeded 21V. Wouldn't this turn the MOSFET back on, defeating the purpose of the circuit?
2. I'm not sure I understand why the Gate Zener is required at all. The MOSFET's Vgs(max)=±20V. In normal operation, Vgs can never be >18V. If Vin reaches the OV threshold (Vgs=18V), the control PNP turns on, tying Gate to Vin (Vgs=0V). Vgs stays at 0V until Vin falls below 18V and the control PNP turns off again. I'm probably missing something here...
3. Hypothetical: MOSFET Vds(max) is -30V. Assuming the Gate Zener is removed, it appears this circuit does nothing to protect against exceeding Vds(max) if Vin runs away. If I were paranoid about this, I would have to add a crowbar at ~28V as a last line of defense, right? That would require a pretty stout SCR or TRIAC to handle the power to blow a fuse or CB at 28V x 2A.

Initially I figured that using a comparator would complicate things a lot, but I think I may have come up with a good solution. And I got to struggle through the math to set hysteresis! New schematic attached.

Part links: AO3407A / AP331AWRG-7 / MM3Z3V0B

My thoughts on this circuit:

• Eliminates the vagaries of PNP base drive current.
• The AP331 comparator operates up to +36V, so no separate power supply is needed, and +36V is above M1's Vds(max) anyway.
• 500mV hysteresis prevents oscillation of M1.
• M1's Vgs(max) cannot be exceeded.

Any thoughts? How about the shunt caps commented on the schematic?

Thanks again, Ron. You've been a huge help!

 

I have three questions about the current design:

1. MOSFET Vgs(th) is -3V. This circuit will cut off Vin at 18V, but if Vin continued rising, the Gate Zener would create -3V Vgs once Vin exceeded 21V. Wouldn't this turn the MOSFET back on, defeating the purpose of the circuit?

1. When Vin>18V, the PNP shorts out the gate zener.
   

   [*]I'm not sure I understand why the Gate Zener is required at all. The MOSFET's Vgs(max)=±20V. In normal operation, Vgs can never be >18V. If Vin reaches the OV threshold (Vgs=18V), the control PNP turns on, tying Gate to Vin (Vgs=0V). Vgs stays at 0V until Vin falls below 18V and the control PNP turns off again. I'm probably missing something here...

   The zener is a result of my conservative approach to engineering. 18V is too close to Vgs(max) for me to be comfortable with it.[/quote]
   

   [*]Hypothetical: MOSFET Vds(max) is -30V. Assuming the Gate Zener is removed, it appears this circuit does nothing to protect against exceeding Vds(max) if Vin runs away. If I were paranoid about this, I would have to add a crowbar at ~28V as a last line of defense, right? That would require a pretty stout SCR or TRIAC to handle the power to blow a fuse or CB at 28V x 2A.

   I don't have any experience with sizing SCRs for crowbars. you might find an app note on line.

Initially I figured that using a comparator would complicate things a lot, but I think I may have come up with a good solution. And I got to struggle through the math to set hysteresis! New schematic attached.

Part links: AO3407A / AP331AWRG-7 / MM3Z3V0B

My thoughts on this circuit:

• Eliminates the vagaries of PNP base drive current.
• The AP331 comparator operates up to +36V, so no separate power supply is needed, and +36V is above M1's Vds(max) anyway.
• 500mV hysteresis prevents oscillation of M1.
• M1's Vgs(max) cannot be exceeded.

Any thoughts? How about the shunt caps commented on the schematic?

Thanks again, Ron. You've been a huge help!

Eric

Your comparator looks like it should work, but I only see about 80mV of hysteresis.
Is the comparator readily available? LM393 is a really cheap dual of the same part.

 

When Vin>18V, the PNP shorts out the gate zener.

Oh boy, talk about missing the obvious. Yikes!

Your comparator looks like it should work, but I only see about 80mV of hysteresis. Is the comparator readily available? LM393 is a really cheap dual of the same part.

Hmm... I came up with the resistor values using the equations in this app note, beginning on page 7. I've been through them a few times and I keep getting the same result. Can you point me to a better guide on this subject?

Thanks for the LM393 suggestion. I'm using two of these AP331s in the design, so a dual device makes good sense. I'll check it out.

Thanks.

 

Oh boy, talk about missing the obvious. Yikes!


Hmm... I came up with the resistor values using the equations in this app note, beginning on page 7. I've been through them a few times and I keep getting the same result. Can you point me to a better guide on this subject?

Thanks for the LM393 suggestion. I'm using two of these AP331s in the design, so a dual device makes good sense. I'll check it out.

Thanks,

Eric

See the attachment for the way I design a Schmitt trigger.

 

Thanks for that reference. I'll cobble some parts together, see how it works and report back.

 

After testing this design with my buck regulator project, I've found a solution that works without causing the input caps to oscillate. Final circuit schematic is attached below.

Ron: I can't account for the difference between your method for calculating hysteresis and the one I found, but my original values are working. The only difference I can see is that your guide is for an inverting configuration and mine is non-inverting. Perhaps another difference is push-pull -vs- open-collector output?


Circuit Description:

U1 (precision shunt regulator) provides a 2.048V reference voltage to the inverting input of the comparator, U2. R1 limits current through U1 to 9mA (see Note 4). R2 and R3 divide Vin to the comparator's non-inverting input. R4 provides positive feedback to establish ~500mV hysteresis (see Note 3). C1 provides a "kick" to the hysteresis, ensuring a hard switchover and eliminating any chance of oscillation.

Below ~18V, the comparator's open-collector output is low, holding M1's gate at ground, which turns M1 on once Vin exceeds M1's Vgs(th). Above ~18V, the comparator's output goes high, M1's gate is pulled high by pull-up resistor R5, and M1 turns off, blocking the over-voltage condition. Hysteresis then requires Vin to fall below ~17.5V before M1 turns on again.


Notes:

1. Depending on the over-voltage threshold and Vgs(max) of the chosen P-MOSFET, it may be necessary to add a Zener diode parallel to R5 (cathode at M1 source, anode at gate) to protect against exceeding Vgs(max).
2. Over-voltage protection is only provided up to the Vds(max) of the P-MOSFET. Above that voltage, MOSFET breakdown may occur.
3. Values for R2, R3 and R4 can be calculated for desired rising and falling threshold voltages using this app note, (page 7).
4. The value of R1 will vary with max Vin. In this case, 1.78kΩ limits current through U1 to 9mA at Vin=18V. The LM4040CIM3-2.0 has a maximum forward current rating of 10mA and maximum reverse current rating of 20mA.

 

Yeah, you're right. I had the input voltage on the inverting input pin. My bad.
My calculations weren't wrong, but my topology didn't match yours.
Your hysteresis at the +input is only about 56mV, but the input signal is attenuated by a factor of (36k+280k)/36k≈8.8, so when you multiply that by the 56mV, you get your 500mV of hysteresis. That's what I failed to account for when I analyzed your circuit the first time.