Help me please!!

Discussion in 'Homework Help' started by ah_gal06, Jan 1, 2008.

  1. ah_gal06

    Thread Starter New Member

    Jul 22, 2007
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    i have a few qns for D Flip Flop..
    1. if the clock is low, how it will affect the output?
    2. if D is connected to NOT Q, what does it mean?

    thanks a lot!
     
  2. Dave

    Retired Moderator

    Nov 17, 2003
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    Nothing will happen, the D-type flip flop is edge-triggered - in the absence of a clock edge the output will remain the same.

    On successive clock-edges the input D and output Q will switch from one state to another, i.e. 0-1-0-1-0-1....

    Dave
     
  3. hgmjr

    Moderator

    Jan 28, 2005
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    The end result of this connection scheme as dave has so ably stated is that the output of the latch divides the incoming clock signal by two.

    hgmjr
     
  4. ah_gal06

    Thread Starter New Member

    Jul 22, 2007
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    huh? what is the meaning of divides the incoming clock signal by 2??
     
  5. beenthere

    Retired Moderator

    Apr 20, 2004
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    The outputs will change state at half the clock frequency.
     
  6. hgmjr

    Moderator

    Jan 28, 2005
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    Oooppppssss!

    Beenthere is correct. I should have used the term frequency in my reply.

    Sorry for the confusion my omission may have created.

    hgmjr
     
  7. ah_gal06

    Thread Starter New Member

    Jul 22, 2007
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    does it mean that NOT Q will send signal to D then Q will follow D?

    sorry if i make u guys confuse.. the image is in the attachment. can u explain to me how the circuit works?
     
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  8. hgmjr

    Moderator

    Jan 28, 2005
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    Based on the diagram you have supplied, you can expect the Q output to change state with each depression of the switch. Some provision for de-bouncing the switch will need to be provided.

    hgmjr
     
  9. Dave

    Retired Moderator

    Nov 17, 2003
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    Yes, but Q will only follow the change on D at the clock edge - this is a fundamental feature of flip-flops that differentiate them from other such devices such as latches.

    For example: D is at 1 and at the clock-edge Q goes to 1 and NOT-Q goes to 0 - this 0 is fed back to D, however Q does not follow D and go to 0 until the clock changes again. It is a cyclic process that alters every time the clock changes.

    Dave
     
  10. ah_gal06

    Thread Starter New Member

    Jul 22, 2007
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    0
    ok i think i understand.. thanks a lot for ur help! :D
     
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