Help me in verilog coding

Discussion in 'Embedded Systems and Microcontrollers' started by nitheeshnas, Jan 21, 2014.

  1. nitheeshnas

    Thread Starter New Member

    Jan 21, 2014
    1
    0
    hiii....i am doing a project on ic design for speed control of a dc motor....here i am adding the verilog code for 3 modules counter,pid and pwm...plzz help me to link these three modules....in such a way that i want the output of counter to be given as the error signal input of pid(e_in) and the out put of pid (u_out) as the the input of pwm(switches)....plzz help....thanks in advance.

    .
    Code ( (Unknown Language)):
    1. module count(clk,a,out,r,n,e);
    2. input clk;
    3. input a;
    4. input [7:0]r;
    5. input [7:0]n;
    6. integer counter=0;
    7. output reg [7:0]e;
    8. output reg [7:0]out;
    9. reg [7:0]temp;
    10. always @ (a)
    11. begin
    12. if (a==1) counter=counter+1;
    13. temp=(counter/r);
    14. out=(temp*n);
    15. if
    16. (out>=200) e=out-200;
    17. else
    18. e=200-out;
    19. end
    20. endmodule
    21.  

    Code ( (Unknown Language)):
    1. module PIDdddd(u_out,e_in,clk,reset,u);
    2. output signed [15:0] u_out;
    3. output signed [15:0] u;
    4. input signed [15:0] e_in;
    5. input clk;
    6. input reset;
    7. parameter k1=107;
    8. parameter k2 = 104;
    9. parameter k3 = 2;
    10. reg signed [15:0] u_prev;
    11. reg signed [15:0] e_prev1;
    12. reg signed [15:0] e_prev2;
    13. assign err=(e_in/5);
    14. assign u =(u_prev)+(k1*err)+(k3*e_prev2);
    15. assign u_out = u+(-(k2*e_prev1));
    16. always @ (posedge clk)
    17. if (reset == 1) begin
    18. u_prev <= 0;
    19. e_prev1 <= 0;
    20. e_prev2 <= 0;
    21. end
    22. else begin
    23. e_prev2 <= e_prev1;
    24. e_prev1 <= err;
    25. u_prev <= u_out;
    26. end
    27. endmodule

    Code ( (Unknown Language)):
    1. module pulse(clk,switches,pwm);
    2. input clk;
    3. input [16:0] switches;
    4. output pwm;
    5. reg pwm;
    6. reg [15:0] counter=0;
    7. parameter sd=195;
    8. always @ (posedge clk)
    9. begin
    10. counter=counter+5;
    11. if(counter<=switches*sd) pwm=1;
    12. else pwm=0;
    13. if (counter>=50000) counter=0;
    14. end
    15. endmodule
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    What do you need help with? It's difficult to know what the goal of each module is; you have code, but I can't tell if the code actually implements the goals for the modules, not considering the coding errors.
     
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