[help]Frequency Lock Loop

Discussion in 'General Electronics Chat' started by abforce, Nov 14, 2013.

  1. abforce

    Thread Starter New Member

    Nov 14, 2013
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    Hi everyone:

    I'm looking for some solution to build a frequency lock loop for my application. I have two sinusoidal signals, one is at 40Mhz and the other is 60Mhz. I want to achieve an output which can switch between the frequencies between these two signals while still remain the phase information.

    I find some frequency-to-voltage-converters but none of them can work at such high frequency. PLL is good if in some way I can keep the phase difference as it is.

    Thank you for any suggestion!
     
  2. TheComet

    Member

    Mar 11, 2013
    88
    12
    Generate the two signals as is, and use an analog switch to select which one goes to the output. I did a quick search, and this IC seems reasonable for what you want to achieve.

    NC7SB3157P6X
    Datasheet

    TheComet
     
  3. abforce

    Thread Starter New Member

    Nov 14, 2013
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    Thank you for help! It can be a good choice for the switch.

    Maybe I just failed to explain the task clearly. The problem I meet now is that I want a THIRD signal to follow the 40Mhz or 60Mhz ones, at the meanwhile not losing its own phase property.
     
  4. crutschow

    Expert

    Mar 14, 2008
    12,991
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    So whats the problem with switching between the two signals for the THIRD signal? The two original signals will still be there. You can add a buffer amplifier for the third signal if you need to drive a low impedance line (such as 50Ω).
     
  5. TheComet

    Member

    Mar 11, 2013
    88
    12
    I don't understand what you're trying to do. Could you explain in more detail?

    Do you need your output signal to be able to switch between 40MHz and 60MHz?
     
  6. abforce

    Thread Starter New Member

    Nov 14, 2013
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    Sorry for my unclear statements.
    The problem is as follows:
    I want a signal to go at 40Mhz at the beginning. When it is 'triggered' it will go up high to 60Mhz and with this change the phase characteristic of the signal remains (different from using a PLL that will lose all the phase information of its own) .
    I want to implement some kind of feedback loop to reduce the phase noise in someway similar with PLL, or anyway that can reduce phase noise in this application.
     
  7. abforce

    Thread Starter New Member

    Nov 14, 2013
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    Sorry for my unclear statements.
    The problem is as follows:
    I want a signal to go at 40Mhz at the beginning. When it is 'triggered' it will go up high to 60Mhz and with this change the phase characteristic of the signal remains (different from using a PLL that will lose all the phase information of its own) .
    I want to implement some kind of feedback loop to reduce the phase noise in someway similar with PLL, or anyway that can reduce phase noise in this application.
     
  8. MikeML

    AAC Fanatic!

    Oct 2, 2009
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    If there is a single VCO that is being frequency stepped from 40MHz to 60MHz (as in a PLL), what does it mean to say that the phase is "different"? IMHO, a VCO will not have a discontinuity, but will take a finite time to settle on the new frequence, sweeping the intermediate frequencies as it goes..

    Are you concerned about a discontinuity in the instantaneous voltage of the signal? If switching between two free running oscillators, obviously, their relative phase could be constantly changing, and there could be a step discontinuity as the switch happens.

    How about Phase locking a 40MHz VCO to a 60MHz XO (divide 60/3 and 40/2) and then switching only at zero crossings?
     
  9. abforce

    Thread Starter New Member

    Nov 14, 2013
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    Yes, that's the point. I tried to use a single VCO, it just works fine, the only problem is that I'm trying to reduce the phase noise it has. The switching point is the information I want to get so that the phase can not be controled.
     
  10. MikeML

    AAC Fanatic!

    Oct 2, 2009
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    Are you talking about the intrinsic phase noise the VCO has at any frequency, or are you talking about a pertubation in output phase caused by the input logic signal as the VCO is commanded to step?
     
  11. abforce

    Thread Starter New Member

    Nov 14, 2013
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    Both of them. So I want a feedback loop to reduce the intrinsic phase noise and a switched reference frequency to reduce the logic noise. The problem is that I can not find suitable way to make feedback due to frequency.
     
  12. MikeML

    AAC Fanatic!

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    So how about a "traditional" PLL where the input logic signal just switches a frequency divider from divide-by-three to divide-by-two, using a phase comparitor and a 20MHz master XO. The PLL loop filter will control the phase noise while the output is resting at either frequency. The sidebands created by the modulation are what they are; I dont think there is much you can do about it..
     
  13. abforce

    Thread Starter New Member

    Nov 14, 2013
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    Thank you! That's a really brilliant idea! But I don't have any acknowledgement about the switching point behavior, should it be in a way predictable?
     
  14. MikeML

    AAC Fanatic!

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    It can be analyized mathematically, but it is complicated. You could add a little bit of logic in the modulating logic signal path that would sychronize the switching time with when the 60/40 signal crosses zero. That might constrain the gyrations that the output goes through on its way from one freq to the other.

    This also brings us back to my other idea. Lock the 60MHz signal to the 40MHz signal using a PLL. Use a high quality XO for the 40MHz signal (one with low jitter phase noise). Then switch between the 40MHz and the 60Mhz output at the instant of time when both signals are at a zero crossing. This adds a little bit of delay to the switching times.
     
  15. abforce

    Thread Starter New Member

    Nov 14, 2013
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    Yes, thank you for your reply! Really help a lot! I will try it.
     
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