# [HELP] D Flip Flop understanding

Discussion in 'Electronics Resources' started by Aresden, Jan 5, 2012.

1. ### Aresden Thread Starter New Member

Nov 11, 2011
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0
Hi guys I have abit of problem understanding the DFF when connected like this.
Assuming clock is activated and Q is initially 0, why would it stay at 0?
Why would it go to logic 1 and hold at logic 1 when the pulse switch (PB_DPST) is pressed?
Help greatly appreciated, many thanks

2. ### MrChips Moderator

Oct 2, 2009
12,440
3,361
Firstly, make sure -PR and -CLR are both connected to logic HIGH.

I am not sure that I understand your questions.

A flip-flop is a sequential circuit (as opposed to a combinational circuit) where the element of time and the sequence of events come into play.

You need to know and understand the truth-table of a D flip-flop (specifically a 7474 type. Not all flip-flops are the same).

Q = D after the LOW-to-HIGH transition of CLK.

What else can it do? Since there are no transitions, Q will remain at 0.

No. Q will assume the state of D on the LOW-to-HIGH transition of CLK.
Hence you should observe a change only after the push-button is pressed and released.

In this case, since D is connected to -Q, the flip-flop will toggle between 0 and 1. (You have created a T flip-flop).

(This is a simulation. With a real circuit you will observe random behaviour because of a phenomenon called switch bounce.)

3. ### Aresden Thread Starter New Member

Nov 11, 2011
3
0
thx for the help mrchips, however I still have questions in red

4. ### MrChips Moderator

Oct 2, 2009
12,440
3,361
At start up, Q can be either state, 0 or 1.

If D = 0 -> Q = 0 after LOW-to-HIGH CLK. Hence -Q = 1

Now,
D = 1 -> Q = 1 after LOW-to-HIGH CLK. Hence -Q = 0

Hence Q will change state, 0..1..0..1..0..1... on every LOW-to-HIGH transition of CLK.