Hi Guys,

I have a design that uses 4 x p-channel mosfets in parallel to share a load up to 80 amps. They are driven by a single source with a frequency of no more than 500 hz. But even at 65 Hz, the design generates a great deal of heat.

I have been using a similar design using n-channel mosfets, that has worked fine. The heat peaks well below acceptable threshold even at 100 amps. I'm using the same basic circuit board design with the only change being the p-channel fets and of course the drive circuitry.

With the n-channel, I used mosfet driver chips, one for each pair of mosfets. Each pair of fets is on opposite sides of the pcb. They attach to the sides of the case which is a big aluminum heat sink.

I suspect my drive circuitry is at fault, or perhaps my selection of mosfet chip, which was selected based on lowest on resistance in its class. I'm no EE so was hoping someone could help me figure out how to reduce the heat on this design.

Does anyone have an idea on what I need to improve to reduce the heat generated?

Thanks.

 

With the n-channel, I used mosfet driver chips.

You named your own problem. A driver chip can dump an amp in a microsecond. A single transistor doesn't stand a chance compared to that.

 

Even worse, when the NPN turns off, the gate charge of the PFET has to be dissipated though R16 + R18. That is the slowest transition that the PFETs are subjected to. The turn on is not much better, the gate charge of the PFET has to be sourced by R18. Each cycle of turning on/turning off is what heats the PFET. Switching at the lowest possible rate will help.

 

Use N-channel MOSFET whenever you can, as P-channel gate charge requirements are about 2-1/2 times higher for an otherwise identically complementary N-channel MOSFET.

 

As #12 said, you'd be much better off using a mosfet driver... or at least do what Mike's implying (to lower all the gate's resistors values, and R5 and R16) and then reconfigure that transistor switch as a totem-pole pair, instead of just a single transistor. That way discharging of the gates would be much faster. But the best way to solve your problem is to do as #12 says.

 

Thanks for all replies.

I would like to use a driver chip. However, the load can be either 12 or 24 volts nominal. Actual would be about 12 - 27 volts. So, that's why I'm using the zener diodes to set the gate voltage. Maybe I'm missing something, but I don't think I can use a driver chip unless Batt+ is a fixed known amount. Please please correct me if I'm wrong on this point.

A totem pole would help, thanks. I'll throw that in the sim and see what it looks like. I'll also try lower resistors.

N-channel isn't an option for this design. I do have a successful N-channel design already.

PS to #12: Who are the Bucs going to pick? I lived in the Tampa area for 25 years and am still a Bucs fan.

 

How about this one?
32 volts, works with ttl input, n-ch pull down at 1.5 ohms...?

 

I'm missing something really basic here.

These FETs are p-channel. They are driven by supplying a voltage of 10V below the supply voltage, which can be in the range of 12-27 volts. So the output of the driver would have to be either Vs or Vs - 10V. This chip supplies either Vs or ground. Again, am I missing something?

 

Yeah. I think a zener diode gate to source to keep the driver from jerking the gate out of the p-ch mosfet and a current limiting resistor to keep the driver from smoking the zener.

I'll go make a drawing, but I'm not promising I can make this work.

 

Can you get the resistors high enough to protect the zeners but low enough to drive the gates quickly?
I don't think so. That's about 25 ma with a 1/4 watt zener.

 

Ok, I get it now. Thanks. I'll dig into that...

 

It's the range of Vcc that's a problem. You can't just stick a zener in there, you have to hang the driver from Vcc and that queers the ttl input. Maybe hang the driver from Vcc and back up a stage to change the input to the driver?

 

How about using a driver plugged to a floating dc-dc converter? Such as this one by @JDT. This driver should work for both p and n mosfets, I think.

 

MC34151 is the part number. It's a bipolar driver and the opto-coupler is a great idea, too. That cures the ttl coupling problem.

 

Sorry for the long silence. But I've been busy in the meantime.

I put together a totem-pole version of the driver and scabbed it in to my circuit board. On the simulator, the circuit has a rise time of about .6 uS. The fall time is about 1/2 of that. When I ran the circuit, the rise time was closer to a full 1 uS. But that's still about 1/15th of the rise time of the previous circuit, which also had a significant fall time.

But the chips are still getting extremely hot. Even when running fairly low amperage (12 amps per chip), the temp keeps climbing relentlessly until I have to turn it off.

I have some FET drivers coming, and I will test them when I get them.

 

P-Ch Datasheet

 

Sorry, I'm not getting why you gave me that. I certainly have it. Is there something you think I missed in there? The gate threshold voltage is at least -2 and can be as much as -4.

After some more testing this afternoon, I'm thinking the problem is elsehwere in the circuit. The output terminals were hotter than the mosfets (which were measure right where they contact the heatsinks). The output terminals were 15C hotter. I looked into procuring a thermal imaging camera this weekend. I'd like to watch this thing warm up and make sure the problem I think I have is the problem I really have.

 

Ignore last post. There was a loose bolt causing the heat.

The circuit is much better with the totem pole gate driver design. I made up some boards for 2 IC gate drivers and will see if that improves things further.

 

Ignore last post. There was a loose bolt causing the heat.

How can a loose bolt be the cause of heat? was that bolt responsible for holding the heat sink in place?... just curious...

 

Sorry, I'm not getting why you gave me that. I certainly have it.

Yes, you have it, but nobody else has it. We can't read your copy from here.