HDMI - Inter/Intra Pair Skew - Inter pair synchronization

Discussion in 'General Electronics Chat' started by Skeebopstop, Oct 17, 2012.

  1. Skeebopstop

    Thread Starter Active Member

    Jan 9, 2009
    358
    3
    Dear All,

    I have been looking in great detail into some HD protocols lately and have a question about the HDMI specification allowable skew requirements.

    Effectively, HDMI allows for (assuming 165 MHz pixel clock - i.e. 1920x1080p) up to 3nS (actually more as I'm ignoring the source skew and only considering cable + sink [i.e. receiver]). For a 165MHz pixel clock, this means 165MHz * 10 (TMDS bit length) data rate (i.e. 1.65 GBit/s). HDMI using TMDS uses the pixel clock to help 'synchronize' the clock recovery circuit which operates on all 3 data transmission channels.

    3nS * 1.65 GBit/s ~= 5 bits.

    So the implications here are that from Data CH1 to Data CH2 to Data CH3 there can be a 5 bit misalignment due to skew. This doesn't seem unreasonable but I can't find anywhere in the spec for persons implementing receiver modules in FPGAs for example how this is to be managed. Perhaps it is just trivial and it is specified to ensure no more than a 5 bit (out of 10 bits) misalignment such that you always know to apply the data to the front half of the 10 bit stream amongst all channels to allow for easy synchronization.

    Anywho, just curious if anybody knew the specifics of why this is allowed in such protocols (i.e. HDMI/DVI).

    Cheers,

    Skeeb
     
  2. ifixit

    Distinguished Member

    Nov 20, 2008
    638
    108
    To align gigabit data streams, the bit streams first enter 5 bit deep fifo buffers. The first bits to arrive are held in there respective buffers until the first bits of all the streams have arrived and then all are clocked out together into the receive decoder at the same time after that intial alignment is done. De-skewing can be done every frame if required since the framing pattern starts with a one preceded with zeros.

    These methods are required because ICs, PCB traces, cables, and cable connectors cannot be made repeatable with exactly the same delays. Even data path delay can vary in the same cable when the cable is coiled as apposed to being laid straight out. There are variations between manufactures and over temperature as well.

    Choose an FPGA that offers this complex interface already built in to it.

    Have fun,
    Ifixit
     
  3. Skeebopstop

    Thread Starter Active Member

    Jan 9, 2009
    358
    3
    Thanks for that ifixit!

    How about that, 5 bits seems the magic number! Now the skewing requirements all make sense.

    I've never done high frequency stuff but am at a new company which eats and breaths it and I'm quite excited. Fun stuff.
     
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