If I'm following the schematic, the 1k and 10k are forming a voltage divider. If using a DPDT center-off switch, when in center off position, the Pmos is partially on with about 2.2 volts on the gate.
The Nmos will have about 21.8 volts, on the gate.
I think a re-design is in order.
The Nmos will have about 21.8 volts, on the gate.
I think a re-design is in order.