Having a problem with H-Bridge Chip

Discussion in 'The Projects Forum' started by Domophone, May 6, 2016.

  1. Domophone

    Thread Starter Member

    Sep 10, 2013
    42
    0
    Hi Guys,

    I'm using ZXMHC10A07N8 to alternate a current through a resistive load. The IC is an 8 pin package containing 2 N channel and 2 P channel MOSFETs.
    Datasheet is here: http://www.diodes.com/_files/datasheets/ZXMHC10A07N8.pdf

    I've uploaded my current SPICE model, where you can hopefully see the problem. The H-bridge appears to be shorting itself due to the PMOSFETs slow turn on time upon powering up the circuit. (in my spice model as U1, pin 3 and pin 7)

    The first IC is used as the H bridge, a second identical IC is used for its n-channels to control the p channels on the first IC. This is because my incoming driver signal is a pulsed 5V and my H-bridge Voltage is 24V. The P channels have pull-up resistors to Vin (24V). The smaller I make these Pullup resistors, the faster the turn on times. I don't really understand why this is, as the MOSFETs seem to all have low gate charges. Any explanation that could help my understanding would be hugely appreciated.

    If anyone could offer some guidance as to what is wrong with the current circuit, I would be thrilled. I've spent all morning trying to figure out what is going on without much progress.

    I've probably forgotten to include something crucial, so let me know.

    Thanks so much,
    Dom

    I've also included the spice model for the IC as I cannot remember how to include it directly in the SPICE file.
     
  2. crutschow

    Expert

    Mar 14, 2008
    13,003
    3,232
    With the 3.5nC gate charge of the P-MOSFETs, the gate voltage rise and fall times should be less than 1 μs with a 1kΩ pull-up.
    What are the times you are observing?

    You're using a 5V gate to drive a 24V pull-up which will not work properly.
    The output needs to be capable of driving 24V, such as a transistor buffer.
     
  3. Domophone

    Thread Starter Member

    Sep 10, 2013
    42
    0

    I cannot actually measure the P-MOSFETs rise and fall times, as the circuit overheats and fries the transistor before a measurement can be taken. I just observed the phenomenon in SPICE and was wondering why i'm observing this. I've attached an image from the SPICE simulation
     
  4. Domophone

    Thread Starter Member

    Sep 10, 2013
    42
    0
    So one issue I found, was the usage of 24V when max Vgs is specified at -20V. The problem persists in SPICE even if you drop the voltage down to 18V though. Going to replace the fried mosfet and re-run it on 18V to see what happens.

    Edit, Replacing 1/2 of the 2nd IC with discrete pmos transistors solves the problem. Any idea why i cannot use half of an IC in this circumstance?

    Edit 2: Tying the unused gates to the unused source seems to have solved the problem in SPICE, will test IRL now. Should have known better than to leave floating gates
     
    Last edited: May 6, 2016
  5. crutschow

    Expert

    Mar 14, 2008
    13,003
    3,232
    I already told you why is doesn't work.
    The gates in the simulation are ideal models set for a 5V output, and thus they won't drive the 24V signal you need for the P-MOSFET gates.

    What gates are you using in your real circuit?
     
  6. Domophone

    Thread Starter Member

    Sep 10, 2013
    42
    0
    I'm confused, If you look at the circuit, the 5V output drives the gate of an n-mos (on the second IC) which has its drain tied to 24Vdc through a 1kOhm resistor. The drain of this nmos drives the pmos gate, so when the pmos is off Vgs(pmos)=0V when on Vgs(pmos)=-24V. Is this not correct? The 5V only drives the NMOSFETs directly, it is buffered via an NMOS for the PMOSs
     
  7. crutschow

    Expert

    Mar 14, 2008
    13,003
    3,232
    Okay, I missed that because I don't have the package model for the MOSFETs in LTspice.
    Post a picture of your schematic.
     
  8. Alec_t

    AAC Fanatic!

    Sep 17, 2013
    5,794
    1,103
    Your FETs are frying because of shoot-through.
    Swap the connections to upper P1g and P2g. When N1 is on, P2 should be on (P2g low), not P1 as you have it.
    Also, upper P2g should be driven by lower N2d (not by lower P2s).
     
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