Hardware for Performing BCH Encoding and Decoding

Discussion in 'Embedded Systems and Microcontrollers' started by thomaskuhn, Nov 2, 2012.

  1. thomaskuhn

    Thread Starter Member

    Jan 21, 2009
    20
    0
    I am looking for some quick advice regarding the cheapest way to implement a BCH (252,128) encoder and decoder and "shall be a truncated (255,131)". I posted a similar question in the general forums a while back, but I wanted some more specific information on performing BCH encoding and decoding using the following:

    1. A PIC Micro controller (ErnieM sugested a PIC18F66J11)
    2. ARM processor on an SBC (Cortex A8)
    3. COTS encoding/decoding chip set

    I am not a mathematician and only barely grasp the concepts of BCH, but the task the hardware would have to do is:

    1. perform BCH error correction on a 2400bps message header (128 data bits, 128 bits parity) of a message
    2. modify one of the bits
    3. Generate a new BCH parity
    4. Update the message header
    5. stream out the message

    Outgoing traffic
    same thing as above except no need to check for errors

    I would like a target for incoming translation to be done in under 65ms.

    It has been strongly sugested to me that a microcontroller such as the one mentioned above might be able handle this. This is the prefered solution that I am seeking, vs a full ARM Cortex single board computer as others have suggested. Thoughts?

    It seems that BCH is used in other places such as CD players and Pagers according to Wikipedia. Are they using a COTS chip to perform this. That might be the easiest solution, just solve it with a little more silicon. I would still need to use the MC for other IO tasks.
     
    Last edited: Nov 2, 2012
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