Hi All,

I have already raised this question but never really got the answer I was after so hoping to raise it again, this time attaching the circuit.

Just to summarize the intent, when the lower FET of U$2 is switched, C4 is allowed to charge. C4 is then intended to provided the gate driver in U$1 for the upper FET power through some cycles while the lower FET remains off.

This is for Class D audio and what I am yet to understand when sizing C4, is how to accomodate for instances where the lower FET is 'off' for longer periods of time and the upper FET is demanded to do quite a few on/off switchings. Any reference I have found for sizing this 'bootstrap' capacitor in half-bridge topologies, don't really seem to account for this. Mind you they do multiply by about a 20x safety factor, after you calculate how much charge it would need to drive the circuit and switch the upper FET on once. I just feel that 20x may be too small if for example the upper FET must be turned on and off 300x for a given upper half of the sinusoid http://en.wikipedia.org/wiki/FileWM,_3-level.svg.

I'm sure my C4 cap is big enough, I have referenced a similar design from International Rectifier and they only used 0.33uF, but I just hate not understanding before I proceed.

Cheers,

 

One or the other cap is going to die. You can NOT back bias a electrolytic that way, they can't take it. Don't parallel, series.

Me, I'm trying to understand why this works (if it does).

 

If I'm correct the bootstrap provides the voltage (and current) to load the gate capacitance of the upper FET. So the bootstrap size depends on the gate capacitance of the high side FET. The bigger the gate capacitance, the more current flows in every switching cycle. The voltage of the bootstrap capacitor has to be higher tan the FET's threshold voltage to turn it on (or better yet: higher than the "fully on" voltage of the FET, to make sure the on-resistance is low). So basically I would say the bootstrap capacitor has to be such that it can charge the gate capacitance 300-times and still have enough voltage left (normally 12V for power FETs).
I'm not too sure about this, but it could give you a hint.

 

One or the other cap is going to die. You can NOT back bias a electrolytic that way, they can't take it. Don't parallel, series.

Me, I'm trying to understand why this works (if it does).

Where do you think this back biasing occurs? There is one reservoir cap on -50V and one on +50V facing towards power supply GND. The caps are oriented as such.

The bootstrap capacitor I reference, will not ever be back biased.

 

If I'm correct the bootstrap provides the voltage (and current) to load the gate capacitance of the upper FET. So the bootstrap size depends on the gate capacitance of the high side FET. The bigger the gate capacitance, the more current flows in every switching cycle. The voltage of the bootstrap capacitor has to be higher tan the FET's threshold voltage to turn it on (or better yet: higher than the "fully on" voltage of the FET, to make sure the on-resistance is low). So basically I would say the bootstrap capacitor has to be such that it can charge the gate capacitance 300-times and still have enough voltage left (normally 12V for power FETs).
I'm not too sure about this, but it could give you a hint.

Hey mate,

that is exactly it, but my sort of rhetorical question originally, is than how many times should these capacitors expect to have to switch?

If I assume the worst case scenario, given I will modulate at 400kHz, it would look like this?

Modulation frequency = 400 kHz
Lowest frequency in audio = 200 Hz

So if I assume that for some reason the carrier frequency had to switch at its' maximum, i.e. PWM output matches the carrier frequency, for a low bass note:

400000/2*200 = 1000.

(2*200 because it is only a concern during top half of 200 Hz sinusoid).

So when I originally calculated this bad boy for one switch, it was something like 50nF. So 50nF*1000 = 50 uF. There is no way I can stick a capacitance that big on there and expect it to charge in time?

I realize the PWM output will never actually follow the carrier frequency in generating a sine wave, but should I not be assuming so to be safe?

Thanks for assistance

 

Where do you think this back biasing occurs?

I think he ment C6 nd C7. the + side has to face towards the higher voltage. and GND (=0V) is higher than -50V, so they actually are reverse biased! Remember that a certain potential has to be referenced to another potential to get a voltage.

About your bootstrap problem: I don't really get what exactly you are trying to do. Ok, I get you want to modulate an Audio signal on a carrier frequency, but I have no idea how you want to achieve that with your circuit...
in addition: you are dealing with signals here right? so you can use signal FET's with a much smaller gate capacitance. Again I'm no expert in this, but i think there are some fast switching FETs around with gate capacities lower than 1nF.
I just looked for the cheapes n-fet on farnell that holds 60V (ok, maybe in your case it should hold 100V) but nevertheless the input capacitance is as low as 50pF, meaning 1000-times smaller than your currently used fet. like this you can downsize your bootstap cap to maybe 1microF.

 

ooops, yes you are both correct, C6 and C7 are on backwards. My bad, didn't notice.

Please note the original circuit attached is incomplete and only demonstrates the half-bridge and gate driver circuit.

The FETs chosen are for power amplification using class D, so signal FETs are not appropriate.

Note that the FETs chosen are about as good as it gets for switched audio, so gate charge etc.. are all kept to a minimum.

Please also note that there are more charges and currents required of the bootstrap capacitor than just the gate charge of the FET. These were all in my original calculations, which I multiplied by 20 or so and came to about 0.1uF, so I set this up another 10x as I'm unsure of how many times it may have to switch under worst case conditions, which I reckon should give me at least 200 switches under worst case.

So let me rephrase the entire question. How many times do you guys think that upper FET may need to switch under worst case conditions if the switching frequency is 400kHz and the frequency range will be 200Hz-20kHz.

If you feel that under operating conditions, 200x will be plenty, than I should have more than enough capacitance in the bootstrap.

cheers