Graphical procedure to establish the quiescent poi

Discussion in 'General Electronics Chat' started by ajinkyakulkarni87, Oct 26, 2005.

  1. ajinkyakulkarni87

    Thread Starter New Member

    Oct 26, 2005
    3
    0
    Where I can find the articals related to following title?
    Please tell me the answer of this question or tell me the website to
    get the answer related to following.....


    "Suggest a Graphical procedure to establish the quiescent point(Q-point) for
    JFET with voltage divider bias" (6 Marks)


    Thank you
    Ajinkya Kulkarni
     
  2. mozikluv

    AAC Fanatic!

    Jan 22, 2004
    1,437
    1
    hi,

    check this out :D
    http://www.allaboutcircuits.com/vol_3/chpt_5/4.html
     
  3. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    Try this Google Search Criteria. You should get a number of useful matches that will shed light on the subject of load-line analysis for JFETs.

    hgmjr
     
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