gated 4093 astable - initial delay issue

Discussion in 'General Electronics Chat' started by kgstewar, Oct 10, 2012.

  1. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    Hi all,

    I am using a cd4093 as a gated astable oscillator and am encountering the expected issue that the first oscillation is longer than the subsequent oscillations because the timing cap has to charge from 0V, initially. I ran across this solution from Sgt. Wookie re: the same issue for a 555 and tried this on my oscillator (divided my 100uF timing cap into three 33uF, one of which is connected to +V). This gave me the full 99 uF of timing needed but the initial delay was still there. Is a different solution required for the 4093?

    Thanks!

    Kevin
     
  2. Ron H

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    Apr 14, 2005
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    Try this circuit. The transistor clamps the cap to the upper Schmitt threshold voltage until the control input goes high. This makes the first half cycle the same width as all succeeding negative half cycles.
    You may have to adjust the base voltage slightly, depending on the upper threshold of your individual NAND gate. You could add a pot (1k - 10k) in the middle of the divider if needed.
     
  3. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    Many thanks, I will give this a try. I see you used a PNP transitor, but I was wondering if an NPN would work (I have a bunch of 2N3904s, no 2N3906s, but I certainly can order some).

    Thanks again!

    Kevin
     
  4. Ron H

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    Apr 14, 2005
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    You could use an NPN (as a diode), or a diode, instead of the PNP, but it will have no current gain, so every time you change R1 (the timing resistor), you will have to change R2 and R3. If R1 is variable, you must use a PNP.
    I would bite the bullet and buy some 2N3906s. No bench is complete without them.:D
     
  5. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    Ah ok. 2n3906s have been ordered. At five cents each, I splurged and bought fifty :)

    Thanks again, I'll let you know how it goes.

    Kevin
     
  6. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    Actually, one more question: I understand that the 555 and the CD4093 both have an initial delay when used as a gated astable. Are there other chips (e.g. CD4047) that can be used as a gated astable that DON'T have the initial delay?

    Thanks!

    Kevin
     
  7. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    Or perhaps using a CD4011 instead of a CD4093? Or do all of these chips have the initial delay? Thanks!

    Kevin
     
  8. Ron H

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    Apr 14, 2005
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    Nope, they all have the same problem. This is because, when the gate is disabled, the cap charges all the way to Vcc (+5V in my example). Once the oscillator starts running, the voltage across the cap oscillates between the threshold voltages of the Schmitt trigger (CD4093).
    CD4011 does not have Schmitt trigger inputs, so a minimum of two gates (3 to guarantee oscillation) is required. The cap voltage still starts out at 5V, but, once the oscillator is enabled, oscillates between two voltages that are well within the supply rails.
    Have you seen AN-118 from Fairchild?
     
  9. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    I had not seen that publication. Very useful. I will stick with my CD4093 oscillator since it requires fewer gates. Thanks!

    Kevin
     
  10. atferrari

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    I recall from "101 circuits" published by Elektor maybe more than 20 (30?) years ago, a circuit that addressed that.
     
  11. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    My parts have arrived and I'm ready to try this solution. For my oscillator, R1 is 47K; C1 is 10 uF; and Vcc is 12V. Do I need to change the values of R2 and R3 or will the values shown still be appropriate?

    Thanks!

    Kevin
     
  12. Ron H

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    Do it like this. The extra transistor is necessary because the higher voltage may break down the base-emitter junction of Q1. Q2 prevents this. You may have to change the value of R2 and/or R3 if your 4093 has Schmitt trigger threshold voltages that differ significantly from those of the spice model.
    Your control signal has to be ≈0V for disable, and ≈+12V for enable.
     
  13. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    Ron H, I tried that last circuit and it works perfectly - no initial delay! Many thanks for all of your help.

    Kevin
     
  14. Ron H

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    OK, great! Thanks for reporting back. Some guys don't.:)
     
  15. mhensell

    New Member

    Oct 8, 2011
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    I don't mean to barge in and forgive me for my ignorance but could you please explain what the PWL symbol in the second schematic is? I'm experiencing the very same trouble as the OP and would like try this myself. Many thanks!
     
  16. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    I think PWL refers to Pulse Width Length, which can be adjusted for this oscillator by varying C and R.

    The last solution that RonH posted worked perfectly for me, so if you are having the same problem I had, give that a try.

    Kevin
     
  17. mhensell

    New Member

    Oct 8, 2011
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    This is a fantastic find. Thanks to both you and RonH. So, we have (2) 2N3906 (all I have are 04's, too :D) R1, 2, 3, and C1? I can't wait to try this. Thanks again!
     
  18. Ron H

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    Apr 14, 2005
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    From the LTspice help file:
    Attached is the .asc file, if you want to run the simulation in LTspice.
     
  19. kgstewar

    Thread Starter Member

    Apr 5, 2012
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    Ha! PWL does NOT mean pulse width length, thanks Ron!

    Kevin
     
  20. Ron H

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    If your supply voltage is not 12V, let me know and I can adjust the resistor values to work with your voltage.
     
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