Take a look at this sim.
On the negative portion of the sine wave the body diode of the top FET conducts driving the center of the 2 FETs negative. Because of this the bottom FET never turns completely off so it burns a lot of power.

 

Take a look at this sim.
On the negative portion of the sine wave the body diode of the top FET conducts driving the center of the 2 FETs negative. Because of this the bottom FET never turns completely off so it burns a lot of power.

Your circuit does not accurately model the OP's circuit.
To do that you need to isolate V1 from V2 and connect V1's common to the MOSFET's sources.

 

Take a look at this sim.
On the negative portion of the sine wave the body diode of the top FET conducts driving the center of the 2 FETs negative. Because of this the bottom FET never turns completely off so it burns a lot of power.

Thanks for the help ron.
I have downloaded the simulation but i am afraid i am not following you.
Why is the gate drive -ve terminal connected to the drain of the lower fet? Should it not be connected to the source?

 

I cant see anything indicating why the lower fet is operating in a different fashion to the upper one.

Once again guys, i really appreciate the help. Coming home from a 10 hour day at university and seeing that people have ideas that may solve my circuit issues is exactly what i need to keep my head in the right place.
Thanks again!
I am not too far from overcoming the biggest obstacle of my project, which is the grief i have had trying to get my mosfets set-up and optimized.

 

Ooops, you guys are right. It should work. Maybe the big gate resistor?

 

I have an answer!

It is the position of the load! When i switch the config so that the lower fets drain is between the load and the source, and connect the upper fets drain directly to the source.
The lower fet is cooler than the upper fet.
Answers! - but no solution thus far.

 

i have narrowed down the issue.
When i use a isolated DC source to drive the gate, the power dissipation is equal as are the temps, however if i connect a capacitor and diode as was done prior - the uneven heating occurs.
I still need to figure out why the load position seems to some into play too.

The image above shows the situation where M2 is getting hotter than M1, when i remove the capacitor and diode, the dissipation is the same and operation is as expected.
I still am not sure what exactly is going on but i will try some more simulations this evening and determine why my cap seems to be discharging through M2.
The 1/4 watt bleeder i had across the capacitor is also rather black, i didn't notice until today.

I think an isolated DC-DC converter is possibly called for with these issues. As was suggested much earlier in the thread.

 

Okay, I puzzled over this for some time but think I figured it out.
The current you are seeing is that required to charge up C1.
After C1 is charged (after a dozen 60Hz cycles or so) then there is no extra current going through M2.
Monitor the current through C1 and the voltage across C1 to observe this.

Of course, when you add the zener load current, you will see some excess current every cycle since the capacitor has to recharge to provide that current.

So, to minimize this effect, you will need to reduce the zener current. One way is to use a series regulator (such as an LM317) in place of the zener to provide the 12V for the circuit operation, which will reduce the current draw to whatever the driver circuit requires.

I see no particular need for an isolated DC-DC converter.

 

My fault Carl for bring lazy and drawing 1/2 a schematic. I think the circuit looks like post 15 so the charge current is pretty low.

 

My fault Carl for bring lazy and drawing 1/2 a schematic. I think the circuit looks like post 15 so the charge current is pretty low.

It's the current through R1 discharging the capacitor that causes the peak capacitor current you are seeing.

 

The one that drives the gates?