Full address decoding?

Discussion in 'Homework Help' started by Naf623, Apr 9, 2014.

  1. Naf623

    Thread Starter New Member

    Apr 8, 2014
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    So I have part of an assignment to "Establish a design for a full address decode circuit for four 256k by 16-bit components connected to a 24-bit address bus, so that the memories are arranged at consecutive addresses beginning at zero".
    Unfortunately I missed the first relevant lecture, and the lecturer's notes are rubbish.
    Am I right to think that lines A0-A15 are common to all chips; A16 & A17 need to go through a 2 to 4 demux to the chip selects; and that lines A18 - A23 are unused and so just all stay as '0's?
    I think the main thing I'm unclear on is what, exactly, the "256k by 16-bit" means: the 16-bit specifically. Is that the number of pins for the address lines, or data lines? What am I supposed to know from being given that info?
     
  2. shteii01

    AAC Fanatic!

    Feb 19, 2010
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    I think the important statement was: I missed the first relevant lecture.

    If there are multiple classes that teach the material, try to sit in with the other class. Or just ask what 256k by 16-bit means.
     
  3. shteii01

    AAC Fanatic!

    Feb 19, 2010
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    Ok. I had to look in my microprocessor textbook.

    I think what you have here is:
    Memory size: 256k Bytes
    Data bus width: 16-bits
    Address bus width: 24-bits
     
  4. MrChips

    Moderator

    Oct 2, 2009
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    Each memory chip has 256k words.
    How many address bits are required to address 256k words?
    How many bits of the 24-bit address bits are not used to address the 256k memory?
    Of these, how many bits do you need to address four banks of 256k memory?
    Each memory chip will have a single CS' (chip select) input pin.
     
  5. Naf623

    Thread Starter New Member

    Apr 8, 2014
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    This doesn't make sense by how the lecturer explained it; he said that the blocks in a memory chip were arranged (or at lest could be visualised to be arranged) in a square where each row was a single word, and then the individual block from that word was selected by way of a multiplexer.
    So is this case 512 words each containing 512 blocks?
    I think its this explanation that's my biggest problem to understand how to solve this.

    Presumably 9 bits to select a word, then another 9 to select the block from the word, so 18?

    Assuming I'm right above, 6.

    2, which I think get decoded/demuxed to the individual chip selects?
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    So visualize it as a square that is 256k on one side and 16-bits on the other.

    You have 256k rows and each row is 16-bits wide.

    You address a row and the chip outputs the 16 bits associated with that row (if you are reading).

    How many address bits are required to enumerate 256k things?
     
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