full adder study question

Discussion in 'Homework Help' started by krpz, Jan 13, 2013.

  1. krpz

    Thread Starter New Member

    Oct 18, 2012
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    Hello, I study about full adder and i have a question,

    from full adder truth table i understand how we take this equations:

    Cout= AB + ACin + BCin = Cin(A+B) + AB

    and

    Sum = A xor B xor Cin = (A'B + Ab') xor Cin (from xor truth table)
    = (A'B + AB')' Cin = Cin'(A'B+AB')

    but after this stage i don't understand which boolean laws we use to have:

    Sum = ABCin+ Cout'(A+B+Cin)

    If anyone could help me?
     
  2. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    From Wiki Full Adder

    The result is
    [​IMG]

    This doesn't quite match what you've written, check your reduction in step 2
     
  3. krpz

    Thread Starter New Member

    Oct 18, 2012
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    [​IMG]

    I want to have the sum as a result of the Cout.
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    But Sum is not a result of Cout. If I tell you what Cout is, are you really claiming that you can tell me what Sum is?

    Is consider the following:

    Cout is 1, what is Sum?

    If you say 0, I will say, really, what about 1 + 1 with Cin = 1?

    If you say 1, I will say, really, what about 1 + 1 with Cin = 0?

    Similar situation if Cout is 0.
     
  5. WBahn

    Moderator

    Mar 31, 2012
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    Whoever came up with that diagram and the claim that it only requires 28 transistors needs to be teaching basic pottery. That circuit, in CMOS, requires 56 transistors and has six unit delays to the Cout output and a whopping nine to the Sum output.

    Using nothing but 2-input NAND gates, a full adder can be implemented using a total of 11 of them, which is 44 transistors, with six unit delays to the Sum output and five to the Cout output.

    A true CMOS implementation of the XOR gates will trim the transistor count to 36 and the speed to four delays for both the Sum and the Cout outputs.

    If want a fast circuit at the expense of transistors, the a direct K-Map implementation will involve 60 transistors but only have two gate delays to the Cout (which is the one you want to be fast) and three to the Sum output. So I can add just four more transistors but make the circuit three times as fast as their proposed solution.

    So I have no idea what point they are trying to make other than you can come up with solutions that are slow and big, but that is very seldom ever desired.
     
    Last edited: Jan 13, 2013
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  6. krpz

    Thread Starter New Member

    Oct 18, 2012
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    Sorry about my english, i mean inside the Sum equation to have the Cout equation as in the picture.

    As for the 28 transistors you can see there:
    [​IMG]

    [​IMG]
    This is from Cmos VLCI Design : 4th edition
    p.431,432
    Neil H. E. Weste
    David Money Harris

    I think when you write 867 pages for these stuff you know if you can do an adder with 28 transistors.
     
    Last edited: Jan 13, 2013
  7. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    If you are in a VLSI Design class, what is your actual question then?

    Are you reducing HDL to hardware, or arranging silicon transistors to optimize for power, speed or space/cost?

    It seems we've either drifted from your original question, or your original question wasn't complete in specifying what, exactly, you'd like to do.

    There is no way to combine S and Cout into a single signal and still claim you have all the information about both S and Cout, unless there is additional information about the bit, such as magnitude/location in a byte. However that option is not even hinted at.
     
  8. krpz

    Thread Starter New Member

    Oct 18, 2012
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    Sorry guys if i confused you, my primary question was:

    This two are logic equations about a full adder:

    --> Cout = Cin(A+B)+AB

    --> Sum = ABCin + Cout'(A + B + Cin)

    I know that Sum = A XOR B XOR C

    and i dont understant how we arrive at the equation where
    Sum = ABCin + Cout'(A + B + Cin)
     
  9. WBahn

    Moderator

    Mar 31, 2012
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    So the circuit he was talking about implementing is not the one you showed, but rather an equivalent circuit implemented in direct CMOS (which is probably what he was referring to when he said "complex CMOS"). I thought the 28 Q was referring to implementation of the circuit you showed using standard CMOS.
     
  10. krpz

    Thread Starter New Member

    Oct 18, 2012
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    No no, i just want to understand the equations, it is nothing to do with the transistor level. I copy a picture so show the gate level implementation because i think i confuse with my first post and then someone says that it cant be done with 28 transistors and i add another reference for this. But i dont care about the transistors if i have the gate level design i know haw to implement with the transistors. The equations are confused me.
     
  11. WBahn

    Moderator

    Mar 31, 2012
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    Let's clean up the notation a bit by using only single letters. So C is Cin and D will be Cout, and S will be Sum. Thus our starting point is

    D = C(A+B) + AB
    S = A XOR B XOR C

    and we are trying to show that

    S = ABC + D'(A+B+C)

    Let's get rid of the XORs.

    S = (A'B+AB') XOR C
    S = (A'B+AB')C' + (A'B+AB')'C

    Now, we could recognize that (A XOR B) is (A XNOR B), or we can get the same result by applying DeMorgan's a couple of times

    (A'B+AB')' = (A'B)'(AB')' = (A+B')(A'+B) = AB+A'B'

    S = (A'B+AB')C' + (AB+A'B')C
    S = A'BC' + AB'C' + ABC + A'B'C

    S = ABC + (AB'C' + A'BC' + A'B'C)

    Do you see the pattern in the parenthesized term? Let's reorder things a bit:

    S = ABC + (A(B'C') + B(A'C') + C(A'B'))

    Now let's add some terms that don't affect anything:

    S = ABC + (A(B'C') + B(A'C') + C(A'B'))
    + A(A'B') + A(A'C') + B(A'B') + B(B'C') + C(A'C') + C(B'C')

    Do you see why every term on the second line is identically zero and, hence, has no effect on the expression?

    Now let's regroup them:

    S = ABC
    + A(A'B') + B(A'B') + C(A'B')
    + A(A'C') + B(A'C') + C(A'C')
    + A(B'C') + B(B'C') + C(B'C')

    S = ABC
    + (A+B+C)(A'B')
    + (A+B+C)(A'C')
    + (A+B+C)(B'C')

    S = ABC + (A+B+C)(A'B' + A'C' + B'C')

    Now let's apply DeMorgans to the last factor of the second term:

    S = ABC + (A+B+C)[(A'B')'(A'C')'(B'C')']'

    Now let's apply DeMorgan's to each of the three factors in the last factor of the second term:

    S = ABC + (A+B+C)[(A+B)(A+C)(B+C)]'

    Now let's multiply out the first two of those same factors:

    S = ABC + (A+B+C)[(A+AB+AC+BC)(B+C)]'

    S = ABC + (A+B+C)[(A+BC)(B+C)]'

    Now let's multiply out the remaining factors in the square brackets:

    S = ABC + (A+B+C)[AB+BC+AC]'

    Finally, let's group them to match D

    S = ABC + (A+B+C)[C(A+B)+AB]'

    Leaving us with

    S = ABC + D'(A+B+C)

    Or, using the original names,

    Sum = ABCin + Cout'(A+B+Cin)

    I may not have written a 900 page book on the subject, but having designed, in part or in whole, a couple hundred full-custom mixed-signal CMOS ASICs over the last couple of decades, I may have learned a few things here or there.
     
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  12. krpz

    Thread Starter New Member

    Oct 18, 2012
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    thank you! much appreciated! you dont imagine how you help me in understanding this! :)
     
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