# Frequency PWM limits and relation in SMPS

Discussion in 'General Electronics Chat' started by nepdeep, Oct 30, 2012.

1. ### nepdeep Thread Starter Member

Sep 14, 2011
139
0
Just started my course on the power electronics....interesting that the output voltage is function of dutycycle and input...but does frequency not infuluence the circuit at all...how do we determine the minimum frequency needed to maintan the output according to the duty cycle...for example if the frequeny of the PWM is 0.1 Hz and the Ton is 10 %, then the power supply would be on for 1 sec and I think 9 seconds will be quite large time to keep the voltage...capacitor would soon discharge...finally producing....not stable dc..but ripple output.....please help me understand the minimum frequency.....and what is it depending on...? Presently I guess...the value of capacitor in parallel??

Dec 14, 2011
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3. ### JMac3108 Active Member

Aug 16, 2010
349
66
I think I understand what you're asking.

The output of a switching supply is a function of the duty cycle, not the frequency. So you're question is basically "what limits the frequency?".

The frequency is limited by practical components. As you already noticed, if the frequency is too low, the value of output capacitance required to hold-up the voltage during the switch off time gets too large.

When the frequency gets too hgh, parasitic losses begin reduce the efficiency of the circuit. Switching converter IC manufacturers are putting out a lot of chips that switch at frequencies of 1-2MHz and even faster. The benefit is that the inductor is smaller at higher frequency, but getting good efficiency can be a real challenge.

Hope this helped

nepdeep likes this.
4. ### nepdeep Thread Starter Member

Sep 14, 2011
139
0
Thanks....its all about tradeoffs and choosing best solution...isnot it?...when frequency is high...we can compensate for low value of inducotOR and capacitor and vice versa...thanks Jmac...