A picture is worth a 1000 words.

what am I looking for ?? SDRAM, VRAM, SRAM, RAMmyhead, should I be looking for ?? My implementation is what is called a ''data buffer'', all data is write and read sequentially.

Just for clarification, when I say write, RAM memory sends current frame to MCU, when I say read, DVI receiver is sending frame to RAM.

Important****I just need one that allows me to write from the chip with a lower frequency writing clock wich will be given by the MCU

I believe FIFO are not deep enough since my write out speed will be almost 20 times less at times. lets say a frame of dvi is 3.93 Mb, (1280*1024*3 bytes), so 3 930 000/24 = 163.75 Kb, each stream of parallel data needs to be near 160Kb deep.

I am just using this as a data rate matcher, my MCU cannot handle the speed of even the lowest resolutions of DVI since many real time calculations are done with the color.

Overflow and lost frames are of no importance, It would be great to start writing out the frame more slowly as it is still being read, but I have no problem just writing out a completed frame, processing with MCU then, clear memory and start read and latch to next new frame.

I hope everybody understand what I am trying to accomplish ??

Best regards,

 

I hope everybody understand what I am trying to accomplish ??

Hoping for somebody to understand is more realistic.
I certainly don't.

 

Probably because you never used ram as is, most people dont use this for everyday projects.

From what I gather, I could use some asynchronous SRAM and a memory controller that works in a sequential way. Or I could use some Flow through synchronous RAM, still reading on these.

The best way, simplest would be deep FIFO, but those chips are 50$

There is no sequential access memory that is 32 bit wide, si I have to overcomplicate things with random access memory and control it sequentially.

 

It would seem that SRAM with the appropriate controller is likely your best choice for the buffer you need. The memory controller could be just an 18-bit counter that goes through the addresses sequentially as the data is written in and then read out.

 

Four 8-bit FIFOs can be connected in parallel to give you a 32-bit word. Also I believe that they can be connected in serial fashion to extend the length of the queue.
This IC is 64 words by 18-bits, so you would need it 2 wide and 1920 deep (wow , that's a lot).
I think using a dedicated MCU would be a lot cheaper.

 

Four 8-bit FIFOs can be connected in parallel to give you a 32-bit word. Also I believe that they can be connected in serial fashion to extend the length of the queue.
This IC is 64 words by 18-bits, so you would need it 2 wide and 1920 deep (wow , that's a lot).
I think using a dedicated MCU would be a lot cheaper.

Too expensive...too big, not deep enough.

FIFO's are way too expensive,

especially the single chip solutions from CYPRESS, who do they think they are ??....CYPRESS!!! GET REAL !!!

100$ for a FIFO chip or a dual pot SRAM are you frikkin kidding LOL !!

 

A thing is worth what a thing will bring.

Your requirements for RAM are completely unclear from your "picture." It tells no story, unless you wish someone to design your circuit for you. Example: if your data is 24 bits wide why do you need 32 to store them?

Oh, and BTW, a RAM that is 32K deep and but a single bit wide will work quite well for your application. You would just use 32 of them.

 

The picture, shows an implementation of a FIFO, not RAM, my understanding was foggy.

32 or 24 chips is out of the question, and I need to hold down 3Mb of data remember, 32*32k= 1Mb.

If you look at the prices and available chips, 24 bits is nearly non-existant and just as expensive. This is supplier strategy to make you buy more than you need.

Crutschow, you seem to be thinking along the same lines as me, that must be the proper way to go.

 

You could use three 256k X 8 SRAMs, such as one of these, to give you 256k X 24 bits.

 

Yeah nice thx.

I'm also looking for some cheap RAM

But I need the old type, wich is not bidirectionnal.

I want an old type thats unidirectionnal. an I and O, not I/O

 

A quick search turned up this which shows several 256K X 4 with separate I/O. Perhaps a larger search would turn up other vendors that produce separate I/O 256k X 8 devices.

 

I think a DMA Controller could do this neatly, integrated or external - are they available?
DMA Controller can be programmed to provide consecutive addresses and control signals at full speed - for one frame, of course, as programmed from the MCU. DRQ can be from clock, maybe, gated for enable/disable.
I dont know whether the clock is present during the blanking intervals. Even if it is, it could be simpler to collect the pixel data, which can be eliminated by uC later.
Of course, all this is for writing to RAM (acquiring a frame from DVI) at full speed and then the data can be processed by MCU at its own pace!

 

Its ok I found the fastest solution for 11$.

6 chips.

 

Could you share it?



Please

 

This is an idea I have wich cannot be discussed here since I'm trying to invent something.

Perhaps if I ever scrap this project I'm sorry.

Its as we discussed, with 6 chips, 1 is a ram block, old and fast.

 

is it a proper cpu with some dram?

 

too high energy useage.