frequency divider verilog (50mhz to 1Khz)

Discussion in 'Homework Help' started by Santa klaus, Jan 19, 2015.

  1. Santa klaus

    Thread Starter New Member

    Nov 16, 2014
    28
    0
    Hi! can somoeone explain this code to me; i know how a frequency divider work but i am new to verilog.
    module Diviseur(clk,rst,clk_out);
    input clk,rst;
    output clk_out;
    reg[15:0] counter;

    always @(posedge clk or negedge rst)
    begin
    if(!rst)
    counter<=16'd0;
    else
    if(counter==16'd5000)
    counter<=16'd0;
    else
    counter<=counter+1;
    end


    assign out_clk = (counter == 16'd5000);

    endmodule
     
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    please use code tags next time
    Code (Text):
    1. module Diviseur(clk,rst,clk_out);
    2. input clk,rst;
    3. output clk_out;
    4. reg[15:0] counter;
    5.  
    6. always @(posedge clk or negedge rst)
    7. begin
    8. if(!rst)
    9.    counter<=16'd0;
    10.    clk_out<=0;
    11. else
    12. begin
    13.    if(counter==16'd5000)
    14.    begin
    15.       counter<=16'd0;
    16.       clk_out<=~clk_out;
    17.    end
    18. end
    19. counter<=counter+1;
    20. end
    21. endmodule
    Is the way I would do it.
     
  3. Santa klaus

    Thread Starter New Member

    Nov 16, 2014
    28
    0
    Thanks. could you please explain what these lines means:
    counter<=16'd0;
    counter==16'd5000
     
  4. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    counter<=16'd0; sets counter to zero
    counter==16'd5000 I think this one asks if counter is equal to 5000 in decimal notation
     
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