frequency divider verilog (50mhz to 1Khz)

Thread Starter

Santa klaus

Joined Nov 16, 2014
36
Hi! can somoeone explain this code to me; i know how a frequency divider work but i am new to verilog.
module Diviseur(clk,rst,clk_out);
input clk,rst;
output clk_out;
reg[15:0] counter;

always @(posedge clk or negedge rst)
begin
if(!rst)
counter<=16'd0;
else
if(counter==16'd5000)
counter<=16'd0;
else
counter<=counter+1;
end


assign out_clk = (counter == 16'd5000);

endmodule
 

kubeek

Joined Sep 20, 2005
5,794
please use code tags next time
Code:
module Diviseur(clk,rst,clk_out);
input clk,rst;
output clk_out;
reg[15:0] counter;

always @(posedge clk or negedge rst)
begin
if(!rst)
   counter<=16'd0;
   clk_out<=0;
else
begin
   if(counter==16'd5000)
   begin
      counter<=16'd0;
      clk_out<=~clk_out;
   end
end
counter<=counter+1;
end
endmodule
Is the way I would do it.
 
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