FPGA state machine implementation of a simple sequential odd parity generator/checker

Discussion in 'Homework Help' started by smerf786, May 2, 2013.

  1. smerf786

    Thread Starter New Member

    Nov 22, 2011
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    In the past we had to create a AND-OR 3 bit parity generator/checker. But im not sure how to do the 7bit. I think I have to use MUX. How would I go about designing it? Do I need a truth table? Im kind of lost. I just need a sense of direction on how to go about doing this. He gave us a state diagram

    Also this is the assignment

     
  2. Papabravo

    Expert

    Feb 24, 2006
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    Hint #1: You don't need an FSM to generate or check parity. It is a combinatorial circuit that can be implemented from any conveniently available gates.
    Hint # 2: The inputs to your FSM are the buttons.
     
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  3. WBahn

    Moderator

    Mar 31, 2012
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    It appears that the intent is to do this sequentially where you are fed one bit at a time.

    So imagine you are the processor and I tell you a 7 bit value but I give you just one bit at a time. You can write down whatever you want, but each time I give you a bit you can only use what you have written down previously plus the bit I've just given you. You want to write down as few things as possible.

    Hint: You can do this by remembering just one bit of information.
     
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  4. smerf786

    Thread Starter New Member

    Nov 22, 2011
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    Like im totally lost. What is my first step here?
     
  5. WBahn

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    Mar 31, 2012
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    If you are totally lost, meaning that you have absolutely no idea how to do any part of this assignment, then your first step is to get a drop slip from your school's registrar's office.

    Otherwise, post your best effort at working YOUR assignment as far as you can.
     
  6. Brownout

    Well-Known Member

    Jan 10, 2012
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    You'll need to shift the bits in your register, and compare them to a value that represents the parity of your value that accumulates with each bit. Does that make sense? As an exercise, write out your data, make it anything, and the write out a shifted value and what the parity would be for each bit as it's shifted out and compared to the parity at the previously shifted bits. See if you can find a pattern.
     
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  7. WBahn

    Moderator

    Mar 31, 2012
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    A useful thing to do is to consider the following question:

    I have given you the first 6 bits of a particular value already and now I tell you that the 7th (and final) bit is a 1. What is the essential piece of information you need to have remembered about those first six bits in order to determine the needed value of the parity bit.
     
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  8. smerf786

    Thread Starter New Member

    Nov 22, 2011
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    I think I figured it out, thanks guys!
     
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