Hello! First off, sorry that my first post is a new thread, but I promise I have searched through the threads tagged with "flyback" and I have not been able to find anything relating to the problem with my project. So...

I am developing a capacitive discharge ignition system. I am looking for a total energy of ~60mJ (or more) per spark event. To achieve this, the 1uF capacitor needs to charge up to ~340V in 1mS. I have been looking at 1” square flyback transformers and I have SPICE modeled a circuit using the parameters of a Coilcraft transformer. I have a sample of the 20A version (GA3459-BL) and I have been trying to replicate the SPICE results with a real circuit.

My problem is that in the real circuit, something is limiting the output voltage to around 120V. It starts the capacitor charging process just like the simulation, but as it approaches 120V, it levels off.

I realize that there are many possible reasons for something like this to happen, and I have gone through several investigations, but now I am stumped. I will attach a document that explains the situation in more detail as well as the tests I have already run and the results.

Any input is greatly appreciated.

Thanks!

 

Can you reproduce the problem in LTSpice and post it here? It is free and is commonly used by many members of this forum.

 

I did the model originally in LTSpice. I have attached it here. There is a text file for the control input which must be in the folder along side the .asc file.

 

Have you looked at the collector turn-off waveform rise-time? If the turn-off is slow, then much of the inductive energy will be dissipated in the transistor instead of being transferred to the secondary. You don't show the gate drive circuit so I can judge if that's adequate.

I'm confused though. Your circuit symbol is for a BJT, but the package pinout shows G D S, which is for a MOSFET. You also show a MOSFET in the simulation, so is Q2 a MOSFET?

 

Q1 is an IGBT (just used to dump the charge so I don't shock myself) and Q2 is a MOSFET (IRF3205). Sorry, I always tend to draw everything as a BJT and I know it is not right.

The gate drive circuit is the direct output of a PIC (5v, 25mA source, 25mA sink). I was worried that it might not be saturating Q2 enough, so for a while I had it switching through a transistor and pulled up to 12V by a 300 Ohm resistor. It looked pretty square and the "voltage ceiling" problem was unchanged when I ran it this way, so I switched back to the PIC output. I will try to post a trace of the 5V signal at the gate of Q2 in a few minutes.

Thanks by the way!

 

what diode do you use in reality?

 

D1 is a Vishay BYG20J.

Attached are some shots of the 5V signal at Q2.

I'm not sure if the low resolution of my scope makes the signal look so blocky or if that is the actual signal shape.

 

The IRF3205 is not a logic level FET so it may not be full on.

 

Those gate signals do not look particularly clean. Can you post the signal from the output of your transistor buffer?

 

I viewed the 5V Q2 gate signal with a bit better scope (attached). It sure does not look very clean. I will swap in the transistor buffer and post a screenshot of the Q2 gate using that in a bit.

 

OK, here is the 12V signal at Q2 with the transistor buffer circuit in place. I had looked at this previously using my USB scope and it looked OK. Clearly I should have been using a better scope.

So, if Q2 is not turning all the way on, it will be reducing the available voltage across the primary winding as it wastes energy heating up. I can see how it will take longer to charge the capacitor up, but I do not understand how it would limit the maximum voltage of the secondary side to 120V or so.

Any theories? In the mean time, I will rummage through my parts for a better transistor for Q2. I have this: IRFPF50? It stands up to 1kV Vce, but it has a max threshold voltage of 4V though, which is the same as my current Q2, so turn on may still be a problem.
I also have this: ISL9V5036S3S, which is an IGBT with 1.5Vce on, so probably can't use it in the final circuit but it has a guaranteed turn on voltage of 2.2V so if the turn on is the problem, this should fix it right?

Any suggestions for the best logic level switched MOSFET that can handle 60A peak pulses?

 

So, I went ahead and swapped in the IGBT for Q2. My thinking was that I know this can be driven directly by the PIC (I have it working this way in many well tested products), and it does not clamp Vce until 390V (Vce should never go above about 40V).

Sadly, it had no effect on the charging circuit. Once again it charged the 1uF capacitor up very quickly at first, but leveled of at about 120V.

 

Even if you use a logic level MOSFET you will still need a buffer driver to rapidly charge and discharge the large gate capacitance of the MOSFET. To see the effect of insufficient drive, change R3 in your simulation to 1k ohm, which may be closer to the drive from your micro.

Below is your circuit driven by an NPN totem-pole driver which seems to work. Noticed that I reversed the switch polarity to allow for the signal inversion from the driver. You might try that driver in your breadboard.

What's the reason for the varying pulse frequency?


View attachment 2013-08-06 - Coilcraft Breadboard (1).asc

 

What's the reason for the varying pulse frequency?

Actually, I was going to ask you guys that. Not to complicate this thread any more, but part of what I am doing with this design is to simplify an existing circuit as much as possible. The existing circuit uses a standard PWM controller that was designed to control a flyback circuit. I have studied it a lot and I always noticed that while it kept the charge pulse time constant, it decreased the "dead time" as the capacitor charged up. When I started simulating the circuit, I found that if I did not leave sufficient time between pulses, not all of the energy would transfer across to the coupled inductor (secondary winding) and when I started charging again the current would jump to some non-zero value and increase from there. Makes sense, secondary resistance and all, but I noticed that the amount of required "dead time" decreased dramatically as the voltage across the capacitor increased. Therefore in order to charge the capacitor as quickly as possible, an increasing frequency control signal can be used. I have just been experimenting with the best set of values so far, both in the spice model and with my test circuit, but at some point I hope to be able to write the transfer function that explains this phenomenon.

 

OK, I understand the reason for the varying pulse period. According to my simulations the Table value OFF period for M1 becomes too short for the energy to be completely transferred to the output capacitor between about 349us to 457us. That interval needs a longer OFF time (when Table PWL =0) for M1 to allow more time for all the energy to transfer to the capacitor. Since, during that interval, some residual inductive energy remains, that shows as a non-zero start value current in the primary.

The phenomenon is due the increasing capacitor output voltage. The inductor has to push its current into the capacitor against that voltage. The time to do that (ignoring the small change is voltage during each charge pulse) is determined by the equation V = Ldi/dt or dt = Ldi/V where V= capacitor voltage at inductor output, L = inductance, di = peak current, and dt = time for transfer. Thus the larger the capacitor voltage, the shorter the time it takes to transfer the inductive energy into the capacitor.

 

Wow! I get scared at the prospect of splitting differentials, but that makes perfect sense to me.

By the way, I did a little more experimenting today with the legacy circuit (the one that does not suffer from the voltage ceiling). I plan to strip it down component by component until it matches my test circuit. I figure somewhere along the way the voltage ceiling will appear and I will get a clue what is causing it. I will report back here with my findings.

 

Did you try the legacy circuit with 1k ohms for the R3 gate input resistor?

 

Hello! First off, sorry that my first post is a new thread, but I promise I have searched through the threads tagged with "flyback" and I have not been able to find anything relating to the problem with my project. So...

I am developing a capacitive discharge ignition system. I am looking for a total energy of ~60mJ (or more) per spark event. To achieve this, the 1uF capacitor needs to charge up to ~340V in 1mS. I have been looking at 1” square flyback transformers and I have SPICE modeled a circuit using the parameters of a Coilcraft transformer. I have a sample of the 20A version (GA3459-BL) and I have been trying to replicate the SPICE results with a real circuit.

My problem is that in the real circuit, something is limiting the output voltage to around 120V. It starts the capacitor charging process just like the simulation, but as it approaches 120V, it levels off.

I realize that there are many possible reasons for something like this to happen, and I have gone through several investigations, but now I am stumped. I will attach a document that explains the situation in more detail as well as the tests I have already run and the results.

Any input is greatly appreciated.

Thanks!

Have you measured the winding resistance of the transformer secondary?

Eric

 

Have you measured the winding resistance of the transformer secondary?

That wouldn't limit the maximum secondary voltage, only the speed at which it reaches the maximum.

 

If you want the most rapid output voltage build-up you might consider a self-oscillating flyback, which uses the core saturation to control the oscillation frequency. That way the frequency/duty-cycle is always optimum without dead-time, and you don't need any external control signals. These circuits normally do require a third winding to control the transistor gate. Here's a simple example, but it does not appear to be self starting. I believe that can be corrected by connecting the input of the first (gate control) winding to V+ instead of ground. Also the dot for the output winding should be on the other end.

To simulate such a circuit in LTspice you will need to use a non-linear inductor model with saturation as explained in the Inductor section in the LTspice Help Topics.