Fluttering Forward Converter with Active Clamp and Sync Rectification

Discussion in 'The Projects Forum' started by Synrec, Oct 16, 2008.

  1. Synrec

    Thread Starter New Member

    Oct 16, 2008
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    0
    Hello All,
    I have designed a Forward Converter with a Primary NMOS FET and a PMOS FET Active Clamp given the following design details:
    1) Input Voltage Range 10V to 30V
    2) Output Voltage Adjustable from (1.5V to 3V @ 3 Amps)
    3) Planar Transformer Parameters
    A) N = 2
    B) Mag Inductance 40uH
    C) Leak Inductanc 0.2uH
    D) Fsw = 400Khz
    E) Duty Cycle Max = 0.7
    F) Transformer High Side Voltage = 13V
    4) Catch Cap = 12000 pF, where my design spreadsheet says it may
    vary between 2000pF min to 19000 pF max.
    5) NMOS and PMOS VDS Max = 55V
    6) NMOS Gate Source Voltage = 13V
    7) PMOS Gate Source Voltage = -13V
    8) PMOS off to NMOS On Delay = 19nS
    9) NMOS off to PMOS On Delay = 62nS (allows primary NMOS switch bounce to stabalize before turning on PMOS)
    10) The circuit is being run open loop with a constant 400KHz Drive with
    40% (On) Duty Cycle. Load is 1.8 ohm resistor
    11) 2ndary Side Inductor is 12uH and Output Cap is 188uF
    12) Using all the above Output Voltage gives 2.02 Volts with 440mV p-p Ripple => Theoretically ripple should be about 33mV max


    Problem: the Catch Cap Voltage flutters from VDS = 13Vp to 55Vp; if I try to take the ouput higher the flutter exceeds VDS Mas of FETs on both primary and secondary side! Also, the FETs and Transformer Run Cool during fluttering. When I try and hook up an R-C network across Catch Cap to damp out oscillation (Lmag and Ccatch Resonance?), it will only stop fluttering after C has been made very large, 0.1uF, and R very small less than 3 ohms. => This sets up the situation where the catch cap has not fully discharged down to VDS before the next NMOS on cycle! Also the primary NMOS FET and R start to get pretty darn warm, obviously losses in R! And is Tranformer fully Reset in this condition (feels like No)?

    Any ideas on how I can get this fluttering to stop and keep the intended design efficiency of 90% or greater? Also is the root cause a Lmag and Ccatch Resonance? Note as a circuit topology reference assume Figure 4 of "Active Clamp Control Boosts Forward Converter Efficiencey" www.Powerelectronics.com. And my circuit does not use figs 6&7 in above design article. It uses UC3714D with PWM controlled by uC and both Output Load Voltage and Current feedback to uC A2D Channels. Closed loop control will be performed by uC as load output power must be adjustable for application!

    Thanks in Advance for ideas/help,
    Syncrec
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
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    A schematic and layout would help. All guesswork otherwise.
     
  3. Synrec

    Thread Starter New Member

    Oct 16, 2008
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    0
    1) Load Voltage and Current Feedback circuitry not shown for IP Purposes
    2) High Res Zoom should work on pdf for subcircuit clarity
    3) I have tried putting a small resistor in series with Cclamp(C130) but it still did not stop VDS fluttering during PMOS on cycle.
    4) Thinking about adding small inductance in series with Cclamp and then large value resistor in parallel with Cclamp! (what do you think?)

    Thanks again,
    Synrec
     
  4. beenthere

    Retired Moderator

    Apr 20, 2004
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    My ignorance has simply overwhelmed me. I have the data sheet for the UC3714 and get no sense of circuit operation from it.

    Very hopefully, someone else with experience will provide some illumination.
     
  5. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    I have never heard of a 'catch' capacitor, which one(s) are you referring to in the schematic?

    Have you considered a snubber on the output of the transformer?

    Steve
     
  6. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
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    scubasteve, that has to be C130 from the value stated. I am unable to say what it's there for, and the two FET's in the secondary circuit with no resistors on the gates make me feel bad.
     
  7. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    This circuit deserves an analysis to understand why it is resonating and presenting a high voltage point on VDS. Have you simulated in it spice?

    I would try to short the input inductance first of all, see if that helps. Then, I would increase your bulk capacitance since ~20uF is not much. I would try about 10X that amount, but if it gives no improvement, then back it off for cost reduction.

    Steve
     
  8. Synrec

    Thread Starter New Member

    Oct 16, 2008
    5
    0
    Hello Steve,

    1) Cc Catch or Clamp Cap: You are correct the Clamp Capacitor (C130) and Catch Capacitor are one and the same. Some of the early design resources I have read called it a catch cap, other resources call it a clamp cap, which is probably more appropriate given the circuit is called "Active Clamp Forward Converter" Circuit.
    2) PSpice: I have simulated the circuit with PSpice, where it does not oscillate. But as we both know it's only as good as the design's weakest components available within the tool, including potential board/design parasitics.
    3) Input Voltage Cap (20uF): Again a design article gives specific equations for minimum input cap value based on the specific design's parameters, in this case the minimum value was calculated to be 2uF => So personally, I resonate with your 10x suggestion when it comes to filtering, especially if it's affordable.
    4) 2ndary side gate resistors or not: Again with design articles and actual implementations of "self-driven synchronous rectification", I have seen the designs implemented both ways. Gut feel, probably not a factor in my present problem unless 2ndary side FET capacitance(s) reflected to primary side is compounding the problem. Not certain, I have never built and tested a circuit like this before, however, in the pursuit of good design practices I will likely implement your suggestion in the search for a solution and in the final design!

    Thank you,
    Synrec
     
  9. beenthere

    Retired Moderator

    Apr 20, 2004
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    282
    One suggestion would be to reduce the PWM frequency and see if things stabilize. 400 KHz sounds like it's pushing circuit response pretty hard. If the sensing is just a bit delayed, then the PWM control could get into oscillation chasing just behind the correct value.
     
  10. Synrec

    Thread Starter New Member

    Oct 16, 2008
    5
    0
    Hello beenthere,

    The minimum frequency of the planar transformer magnetics is 400KHz (upper end 1 MHz). Right now the circuit is being run open loop with the PWM frequency set to 400KHz and 40% Duty Cycle, which keeps the Cc max flutter voltage just below the maximum specs of the FETs.

    Thanks for the ideas - keep them coming,
    Synrec
     
  11. nanovate

    Distinguished Member

    May 7, 2007
    665
    1
    You might need to play with the delays between switching the N & P FETs.
     
  12. Synrec

    Thread Starter New Member

    Oct 16, 2008
    5
    0
    Hello nanovate,
    I have set the P-N-N-P delays all the way from 10s of ns to 100s of ns with no effect on Cc resonance/fluttering. Everything I read says the delays should be minimized, but ensure there is no shoot-thru. Right now the delays are emperically set at minimum values.

    Thank you for idea,
    Synrec
     
  13. Titantony

    New Member

    Apr 7, 2009
    1
    0
    Hello!

    Could it possibly be the value of R94 and C129?. I should try to make the gate driving impedance lower. The MOSFETS are so fast that slightest inductance i serie with the source will have effect.
     
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