Floating core circuit

Discussion in 'The Projects Forum' started by Anticitizen1, Jul 1, 2010.

  1. Anticitizen1

    Thread Starter New Member

    Jul 1, 2010
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    Not so long ago decided to carry out quite new project based on dynamic split/join of processor cores . Idea is that core splits into small cores with lower bits range as program code processed and back. The idea is that program average data bit range is much lower than max 64 or 128 bits of processor width. So it gives opportunity to avoid problems in splitting programs into 2 core or 4 cores. Increase processing of data and instructions.

    Drawback is that there are a lot of new lines for core regulating signals and dependent consequent calculations. Possible problem is that one device should be controlled on the data overflow exception.

    Problems occured with proper parametrisation of all possible combinations.

    Still thinking of model / language/architecture to choose. I had chosen JOP processor for that.
    Want to know what others are thinking?
     
  2. sceadwian

    New Member

    Jun 1, 2009
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    I don't see a way of making a dynamically swapping core in such a manner without using up as much or more space than required for fully separate cores. You're trying to blend software and hardware optimization into a single process which can't occur. things done one way on one type of fundamentally different hardware have to be done a different way on another. If you try to short circuit this by creating an intermediary layer all it's going to do is complicate things and create problems.
    The core hardware architecture of the machine the software is running on is always going to be critically important. You're using FPGA's you don't even have that limitation in the first place.
     
  3. Anticitizen1

    Thread Starter New Member

    Jul 1, 2010
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    A agree that it is complicated, but I dont know if it good to increase number of cores.Because software programmers are almost opressed with that ongoing core assault,I worked in that field and <snip> it is so.It's not a problem to add another core, but it is almost fantastic work to "cut" programm properly.Sometimes programs for single core can work slower if they are cut with mutexes and launched on multicore.
    Yes software is critical - that is a serious issue.

    Same floating core project started 2-4 years ago in California they achieved 2-3 times increase of performance comparatively to stable cores.
     
    Last edited by a moderator: Jul 2, 2010
  4. sceadwian

    New Member

    Jun 1, 2009
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    I'd love to see the project that they did as modern PC software isn't particularly able to be divided up in this manner, let alone the hardware existing that could do it.
     
  5. Anticitizen1

    Thread Starter New Member

    Jul 1, 2010
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    Problem is simulation results which are unpredictable due to numerous core's and time delay combinations.
    My experience of working in assebler (and C++) long ago showed that few % of data width is used.Ok if processor is 64 bit that is 576460752303423487(if all 64 are 1) !!!!How mANY ppl use such numbers? MOST numbers are less tha 16-20 bit.So others 48 - 44 ?

    Thats the key idea of FCU.
     
    Last edited: Jul 8, 2010
  6. sceadwian

    New Member

    Jun 1, 2009
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    The problem being you have to synchronize a core between two states, parallel and series operation, the only way I could see this as plausible is in an FPGA system where the actual logic can be reprogrammed, if you're gonna go that far just teach more people to use the full abilities of an FPGA and make a standard FPGA interface to modern bus systems. There is no true way to address these problems although from a pure research standpoint I think any idea should be given a toss, might teach something.
     
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