Discussion in 'Homework Help' started by ne5pats, Apr 10, 2011.

1. ### ne5pats Thread Starter New Member

Mar 5, 2011
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I need to understand how can i wire J-K flip-flops to produce a binary up count at their Q outputs. Also, what is the advantage of a D-type Flip flop when comparing it to the SR flip flops. i have a test and i really need to understand this. Thanks

2. ### hgmjr Moderator

Jan 28, 2005
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Post a sketch of your effort so far at finding a solution. We can then make suggestions on where you may need help.

In the meantime you will likely benefit from consulting a datasheet on a typical J/K flip-flop. In particular study the published truth table.

hgmjr

3. ### ne5pats Thread Starter New Member

Mar 5, 2011
13
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Here is what i have done so far.

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4. ### beenthere Retired Moderator

Apr 20, 2004
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283
Your clock input to the 7476 goes to a pullup resistor. I don't think that will work. If J4 is left as a short, U1A may get a bit hot.

What are the NAND gate SR flip flops supposed to demonstrate?

5. ### ne5pats Thread Starter New Member

Mar 5, 2011
13
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i put the J/K on the bottom left, but my question is how can i wire J-K flip flops to produce a binary up count at their Q outputs... i am completely lost i wouldn't know how to explain this ... my test is tomorrow and this question was in the review sheet :}

6. ### beenthere Retired Moderator

Apr 20, 2004
15,815
283
What would a binary up count look like on paper? How could you arrange for more than one J-K to produce that output? Hint - one flip flop isn't enough to make a counter.

With J-K flip flops, the state of J & K determine the output on being clocked. D flip flop's outputs follow the D input when clocked. There is a data sheet available for 7476's and for 7474's - use a search engine to find them. The data sheets give all the details about how the devices work.

Nov 25, 2009
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Mar 5, 2011
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thanks alot