For each FF of the following, fill out the truth table and draw the output
waveform, by hand, of Q and showing your work?
Problem1: NAND gate R-S Flip Flop that is initially LOW

My question is what does he mean when he say "initially low" and how this affect on the drawn waveform?

 

You have inputs and outputs. If I remember correctly, the inputs are normally low and change state on a positive edge. What point could start out high or low that you would have to make a choice?

Sorry. I focused on the wrong thing and got this entirely wrong.

 

No, a NAND based RSFF has active LO inputs. Since we are talking about an AND operation, if an input to a NAND gate is HI the other input dictates the output, while if one input is LO it forces the output to a known state regardless of the other input.

 

I didn't get it please help me to solve this homework !
I can't define when we use rising or falling edge for each type to draw the waveform

 

Do you understand what a truth table is?

Each of your homework problems wants you to fill in the truth table and then using that table, sketch the outputs.

 

I wonder about this circuit is it a regular D-flip flop (i,e; response to +ve level) or is it an edge trigger D-flip flop(response to +ve or -ve edge trigger)?
I can't know that for problem 3,4 and 5 !

 

I wonder about this circuit is it a regular D-flip flop (i,e; response to +ve level) or is it an edge trigger D-flip flop(response to +ve or -ve edge trigger)?
I can't know that for problem 3,4 and 5 !

I don't mean to confuse you, but what you've shown is not really a "D" flip-flop...it is a gated SR Latch (with the R driven by an inverter). A true "D" flip-flop has a master-slave configuration and is always edge triggered.

 

I don't mean to confuse you, but what you've shown is not really a "D" flip-flop...it is a gated SR Latch (with the R driven by an inverter). A true "D" flip-flop has a master-slave configuration and is always edge triggered.

OK and the gated SR Latch (with the R driven by an inverter) response to +ve level or to edge trigger?

 

OK and the gated SR Latch (with the R driven by an inverter) response to +ve level or to edge trigger?

I already indirectly gave you the answer. Use your mind. Understand the difference between level and edge triggering, then apply that knowledge to the schematic you posted. Good luck...we're all counting on you!

 

I wonder about this circuit is it a regular D-flip flop (i,e; response to +ve level) or is it an edge trigger D-flip flop(response to +ve or -ve edge trigger)?
I can't know that for problem 3,4 and 5 !

What do you mean that you can't know that? Is it somehow forbidden for you to know that when working the problem?

You are trying to work the problem by throwing cook book recipes at it. Instead, why don't you try doing what the homework is pretty clearly trying to get you to do, namely analyze these digital circuits. Forget that they are called "latches" or "flip flops" or that one input is called "D" and another is called "clock". They are simple digital circuits having a couple inputs, a couple outputs, and a few internal nodes. Treat them as such.

So for Problem #3, for instance, you have three internal nodes. You can call them Bob, Fred, and Sue, but I would recommend calling them Dbar (the output of the inverter), Sbar (the output of the top left NAND gate), and Rbar (the output of the bottom right NAND gate). So add these three signals to your timing diagram (I would place them between Clock and Q) and then work yourself from left to right.

Give that a try and post your diagram if you have problems.

 

I draw the output waveform once for response for edge trigger and another for response for +ve level ....now which one is correct and which one I choose for my H.W ....that's my problem !!!

 

How the hell should we know which one, if either, is correct when you won't show us either? Do you really believe we are THAT good?!

What part of SHOW YOUR WORK do you not comprehend?

As I said before, forget about edge-triggered or level-triggered. It is merely a digital logic circuit with two inputs and two outputs. Analyze it as such.

 

I've drawn the output waveform once by +ve level and another by +ve edge trigger ...now which one is correct and suitable for my H.W .... this is my problem no more no less ..!!!!

 

Actually, it would appear you have much more serious problems than that.

 

Actually, it would appear you have much more serious problems than that.

Are you getting frustrated, WBahn? Hard to tell...

You know, I've been accused here of not being nice sometimes, but I don't think I was ever *that* not nice. Perhaps you may wish to go have a beer and ignore this thread till OP finally decides to post his work (or not)?

Edit: Ha! Imagine that. *Me* moderating a thread. Will miracles never cease?

 

I was being completely straightforward. If the OP thinks he has analyzed the circuit but can't tell if it is level-triggered or edge-triggered, then his problems are much more serious than just needing someone to tell him if it is level-triggered or edge-triggered. He has serious problems performing a basic analysis of a simple digital circuit and that need to get addressed. Until then, he might as well flip a coin to answer his question because his analysis skills amount to guessing anyway.

 

That's what I like about WBahn ... he is straight up, no nonsense type of person.

 

If you tried to attach a drawing, it didn't work. Please try again.

 

here's my drawn for both level and edge ... now which one is correct for the circuit shown in attachments?

 

The point of the problem is for YOU to figure out which one is correct? Or, more accurately, for you to determine whether the circuit presented is level sensitive or edge sensitive. You might as well stop demanding that we just give you the answer to your homework problem. Instead, we will guide you in a direction that will lead you to the discovery of the answer yourself, for that is how you learn best. After all, clearly you do not understand how to analyze this circuit and just telling you the answer is not going to change that.

Now, you can either choose to follow the suggestions that will lead you to the answer, or you can ignore the suggestions. That's a choice you will have to make.

I can at least reassure you that one of your diagrams is correct (which is not something that I knew before you finally posted them). If you will now just simply do the following simple thing, you will be able to determine which one is correct and, hence, whether this circuit is level or edge sensitive.

Add the three internal signals to your diagram. At each transition of one of the inputs, walk the effect of that change through the internal signals and to the outputs.

That's all you have to do. It should take you no more than five minutes.