Flip flop

Discussion in 'General Electronics Chat' started by Khushi, Sep 1, 2014.

  1. Khushi

    Thread Starter New Member

    Sep 1, 2014
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    why do we clock flip flops
     
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    The clock determines the point in time where the data input gets stored inside the flip flop.
     
  3. Khushi

    Thread Starter New Member

    Sep 1, 2014
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    Why can't we just enable the required flip-flops & give them input ? As we change in input, the output changes. Why do we have to change the output with rising or lowering clock edge (in case of edge triggered flipflop)?
     
  4. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    That is called a latch. As long as the enable input is high the latch puts the input straight to the output, and when enable goes low the last value stays on the output.
     
  5. ScottWang

    Moderator

    Aug 23, 2012
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    The clock was designed for data(D) input, the Q value will follow D value when the ck was changing from low to high.
    The s was designed to preset the Q to high, and the r was designed to reset the Q to low.
    Sometimes, if I want a high appear on Q then I will connecting D and ck to low, and using the high trigger signal and via CR differentiator to trig the s, the same way used in r.
     
  6. BillB3857

    Senior Member

    Feb 28, 2009
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    FlipFlops use the clock input to allow precise timing of events. Usually the clock is a common timing event for multiple points in the circuit that must be synchronized with each other. As an example, a ripple counter, without a common clock to all FFs would not have the transitions of the last output lined up with the transitions of the first FF due to transition delay seen in a toggle type FF.
     
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