flip flop propagation delay ?

Discussion in 'Homework Help' started by fran1942, May 11, 2013.

  1. fran1942

    Thread Starter Member

    Jul 26, 2010
    58
    0
    Hello, we have been discussing basic flip flop operation.
    One topic was regarding the use of three inverters to increase the propagation delay. An image was shown which showed three inverters leading into an AND gate with a clock pulse passing through.
    The heading was positive/negative edge generation.

    I am unsure of the purpose of this topic. Was it to show that the rising/falling edges need to be extended to make detection easier ?

    if anyone can please help explain what point was being made here, that would be great.

    Thanks kindly.
     
  2. JohnInTX

    Moderator

    Jun 26, 2012
    2,339
    1,022
    Without a schematic its hard to tell what you are looking at but it sounds like the 2 inputs of the AND are fed by the clock - one directly and one through 3 inverters.

    A starting clock=0 puts a 0 directly on one input of the AND and a 1, through the 3 inverters, on the other. The output of the AND is 0.

    When the clock input goes 0->1, the direct input on the AND is combined with the inverter's 1 (because the delayed clock input has not yet made it through the 3 inverters) and the output of the AND goes to 1.

    3 propagation delays later, the input 1 gets through the 3 inverters making their AND input a 0, resulting in the AND output being 0 again.

    The result is a short (3 * Tpropagation) pulse on the AND's output for each 0->1 transition of the input. After that, the logic level on the input to the circuit does not matter until the next 0->1 transition, hence the term 'edge triggered'.
     
    Last edited: May 11, 2013
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